AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 304
AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
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G
H
I
INDEX-5
Flash Read from Expansion Bus
Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Flash/EPROM Read . . . . . . . . . . . . . . . . . . .94
FLASH_ADDR
FLASH_DATA
FLCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
FLOE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
FLOW
Flow, LAPP . . . . . . . . . . . . . . . . . . . . . . . . .A-2
FMDC Values . . . . . . . . . . . . . . . . . . . . . . .218
FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Frame Format at the MII Interface
Connection . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Full-Duplex Link Status LED Support . . . . .81
Full-Duplex Operation . . . . . . . . . . . . . . . . . .80
General Description . . . . . . . . . . . . . . . . . . . . 3
GNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . .104
I/O Buffer Ground (25 Pins) . . . . . . . . . . . . .31
I/O Map In DWord I/O Mode
(DWIO = 1) . . . . . . . . . . . . . . . . . . . . . . . . .109
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . .107
I/O Resources . . . . . . . . . . . . . . . . . . . . . . .106
IDSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
IEEE 1149.1 (1990) Test Access Port
Interface . . . . . . . . . . . . . . . . . . . . . . . . .31, 103
IEEE 1149.1 Test Access Port Interface
(JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
IEEE 802.3 Frame And Length Field
Transmission Order . . . . . . . . . . . . . . . . . . . .73
IFS1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .59
Initialization Block . . . . . . . . . . . . . . . . . . . 225
Initialization Block (SSIZE32 = 0) . . . . . . .225
Initialization Block (SSIZE32 = 1) . . . . . . .225
Initialization Block DMA Transfers . . . . . . .52
Initialization Device Select . . . . . . . . . . . . . .24
Initiator Ready . . . . . . . . . . . . . . . . . . . . . . . .25
Input Setup and Hold Timing . . . . . . . . . . .272
Flash Address Register . . . . . . . . . . . . . .150
Flash Data Register . . . . . . . . . . . . . . . . .150
Flow Control Register . . . . . . . . . . . . . . .151
Inter-Frame Spacing Part 1 Register . . . .152
P R E L I M I N A R Y
Am79C976
J
K
L
Instruction Register and Decoding
Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
INT0
INTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
INTEN0
Interface Pin Assignment . . . . . . . . . .149, 211
Interrupt Request . . . . . . . . . . . . . . . . . . . . . .24
IPG
IRDY 25
JTAG (IEEE 1149.1) TCK Waveform
for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . 276
JTAG (IEEE 1149.1) Test Signal
Timing . . . . . . . . . . . . . . . . . . . . . . . . .276, 277
Key to Switching Waveforms . . . . . . . . . . . 270
LAPP 3 Buffer Grouping . . . . . . . . . . . . . .A-5
LAPP 3 Buffer Grouping for
Two-Interrupt Method . . . . . . . . . . . . . . . .A-10
LAPP Flow
LAPP Timeline A-4
LAPP Timeline for Two-Interrupt
Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-9
Late Collision . . . . . . . . . . . . . . . . . . . . . . . . 71
LED Control Logic. . . . . . . . . . . . . . . . . . . . 99
LED Default Configuration . . . . . . . . . . . . . .99
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . 98
LED0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LED0 Control Register . . . . . . . . . . . . . . . .158
LED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LED1 Control Register . . . . . . . . . . . . . . . .159
LED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LED2 Control Register . . . . . . . . . . . . . . . .159
LED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LED3 Control Register . . . . . . . . . . . . . . . .159
Legal I/O Accesses in Double Word
I/O Mode (DWIO =1) . . . . . . . . . . . . . . . . . 109
Legal I/O Accesses in Word I/O Mode
(DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Logical Address Filter Register . . . . . . . . . .157
Look-Ahead Packet Processing . . . . . . . . . . . . 2
Interrupt0 . . . . . . . . . . . . . . . . . . . . . . . . .153
Interrupt0 Enable . . . . . . . . . . . . . . . . . . .155
Inter-Packet Gap Register . . . . . . . . . . . . 157
Two-Interrupt Method . . . . . . . . . . . . . . .A-8
8/01/00
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