AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 226

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

and TLEN fields in the initialization block are each 4 bits
wide. The values in these fields determine the number
of transmit and receive Descriptor Ring Entries (DRE)
which are used in the descriptor rings. Their meaning
is shown in Table 99.
If a value other than those listed in Table 99 is desired,
CSR76 and CSR78 can be written after initialization is
complete.
RDRA and TDRA indicate where the transmit and re-
ceive descriptor rings begin. Each DRE must be located
at a 16-byte address boundary when SSIZE32 is set to
1 (BCR20, bit 8). Each DRE must be located at an
8-byte address boundary when SSIZE32 is set to 0
(BCR20, bit 8).
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
226
Table 98. R/TLEN Decoding (SSIZE32 = 0)
Table 99. R/TLEN Decoding (SSIZE32 = 1)
R/TLEN
R/TLEN
1X1X
11XX
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
000
001
010
011
100
101
110
111
Number of DREs
Number of DREs
128
128
256
512
512
512
16
32
64
16
32
64
1
2
4
8
1
2
4
8
P R E L I M I N A R Y
Am79C976
the first bit in the incoming address (as transmitted on
the wire) is a 1, it indicates a logical address. If the first
bit is a 0, it is a physical address and is compared
against the physical address that was loaded through
the initialization block.
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC is used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into mem-
ory.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility
to determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeros and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected. If the
DRCVBC bit (CSR15, bit 14) is set as well, the broad-
cast packets will be rejected. See Figure 4747.
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is com-
pared with the first bit in the destination address of the
incoming frame. It must be 0 since only the destination
address of a unicast frames is compared to PADR. The
six hex-digit nomenclature used by the ISO 8802-3
(IEEE/ANSI 802.3) maps to the Am79C976 PADR reg-
ister as follows: the first byte is compared with
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)
byte is compared with PADR[15:8], again from the least
significant bit to the most significant bit, and so on. The
sixth byte is compared with PADR[47:40], the least sig-
nificant bit being PADR[40].
The mode register field of the initialization block is cop-
ied into CSR15 and interpreted according to the
description of CSR15.
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