AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 52

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Whenever the Am79C976 controller is the current bus
master and a data parity error occurs, SINT (CSR5, bit
11) will be set to 1. When SINT is set, INTA is asserted
if the enable bit SINTE (CSR5, bit 10) is set to 1. This
mechanism can be used to inform the driver of the sys-
tem error. The host can read the PCI Status register to
determine the exact cause of the interrupt. The setting
of SINT due to a data parity error is not dependent on
the setting of PERREN (PCI Command register, bit 6).
By default, a data parity error does not affect the state
of the MAC engine. The Am79C976 controller treats the
data in all bus master transfers that have a parity error
as if nothing has happened. All network activity contin-
ues.
During execution of the Am79C976 controller bus mas-
ter initialization procedure, the Am79C976 controller
52
DEVSEL
FRAME
PERR
TRDY
C/BE
IRDY
CLK
PAR
AD
1
DEVSEL is sampled
2
P R E L I M I N A R Y
ADDR
0111
3
Am79C976
PAR
4
BE
will use a burst transfer of seven Dwords to read the ini-
tialization block. AD[1:0] is 0 during the address phase
indicating a linear burst order.
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the Am79C976
controller will internally discard the extraneous informa-
tion that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7-0) affect the
way the Am79C976 controller performs descriptor read
operations.
Because of the order in which the descriptor data must
be read or written when SWSTYLE is set to 0 or 2, all
descriptor read operations are performed in non-burst
mode. See Figure 2222.
5
DATA
6
PAR
7
8
9
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