DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 110

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pins can be driven with LIU loss. If reset, they
are driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pins with LOS (analog or digital) or
signalling freeze is controlled by GFCR.2. This selection affects all ports.
Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is
an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock
to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is
required for transmit synchronization and IBO operation.
—
7
0
GTCR2
Global Transceiver Control Register 2
0F2h
—
6
0
—
5
0
110 of 273
—
4
0
—
3
0
LOSS
2
0
TSSYNCIOSEL
1
0
—
0
0