DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 84

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

8.12
The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns. It is
used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
Table 8-40
Table 8-40. Registers Related to BERT Configure, Control, and Status
Global BERT Interrupt Status Register
(GBISR)
Global BERT Interrupt Mask Register
(GBIMR)
Receive Expansion Port Control Register
(RXPC)
Receive BERT Port Bit Suppress Register
(RBPBS)
Receive BERT Port Channel Select
Registers 1 to 4 (RBPCS1:RBPCS4)
Transmit Expansion Port Control Register
(TXPC)
Transmit BERT Port Bit Suppress
Register (TBPBS)
Transmit BERT Port Channel Select
Registers 1 to 4 (TBPCS1:TBPCS4)
BERT Alternating Word Count Rate
Register (BAWC)
BERT Repetitive Pattern Set Register 1
(BRP1)
BERT Repetitive Pattern Set Register 2
(BRP2)
BERT Repetitive Pattern Set Register 3
(BRP3)
BERT Repetitive Pattern Set Register 4
(BRP4)
BERT Control Register 1 (BC1)
BERT Control Register 2 (BC2)
BERT Bit Count Register 1 (BBC1)
BERT Bit Count Register 2 (BBC2)
BERT Bit Count Register 3 (BBC3)
BERT Bit Count Register 4 (BBC4)
BERT Error Count Register 1 (BEC1)
BERT Error Count Register 2 (BEC2)
BERT Error Count Register 3 (BEC3)
BERT Latched Status Register (BLSR)
BERT Status Interrupt Mask Register
(BSIM)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
Bit-Error-Rate Test (BERT) Function
shows the registers related to the configure, control, and status of the BERT.
REGISTER
0D4h, 0D5h, 0D6h,
1D4h, 1D5h, 1D6h,
ADDRESSES
FRAMER
110Ah
110Bh
110Ch
110Dh
110Eh
1105h
1106h
1108h
1109h
110Fh
1100h
1101h
1102h
1103h
1104h
1107h
0FDh
0FAh
08Ah
08Bh
0D7h
18Ah
18Bh
1D7h
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BERT alternating pattern count register.
BERT repetitive pattern set register 1.
BERT repetitive pattern set register 2.
BERT repetitive pattern set register 3.
BERT repetitive pattern set register 4.
BERT bit pattern length control.
BERT bit counter.
BERT bit counter.
BERT error counter.
BERT error counter.
BERT Interrupt mask.
When any of the four BERTs issue an
interrupt, a bit is set.
When any of the four BERTs issue an
interrupt, a bit is set.
Enable for the receiver BERT.
Bit suppression for the receive BERT.
Channels to be enabled for the framer to
accept data from the BERT pattern generator.
Enable for the transmitter BERT
Bit suppression for the transmit BERT
Channels to be enabled for the framer to
accept data from the transmit BERT pattern
generator.
Pattern selection and miscellaneous control.
BERT bit counter—increments for BERT bit
clocks.
BERT bit counter.
BERT error counter.
BERT status registers—denotes
synchronization loss and other status.
FUNCTION