DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 155

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in these register are latched. This register does not create interrupts. See
Bit 7: Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI
T1.403 requirements for pulse density.
Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or
multiframe alignment.
Bit 4: Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the
length of the string) have been received.
Bit 3: Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the
length of the string) have been received.
Bit 2: Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in
error.
Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RTIP and RRING
independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding.
Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
RPDV
7
0
RLS2 (T1 Mode)
Receive Latched Status Register 2
091h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
6
0
COFA
5
0
155 of 273
8ZD
0
4
16ZD
3
0
RLS2
for E1 mode.
SEFE
2
0
B8ZS
1
0
FBE
0
0