DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 257

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
Figure 12-8. Transmit Formatter Timing—Backplane
NOTE 1: TSYNC IS IN THE OUTPUT MODE.
NOTE 2: TSYNC IS IN THE INPUT MODE.
NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 5: NO RELATIONSHIP BETWEEN TCHCLK AND TCHBLK AND THE OTHER SIGNALS IS IMPLIED.
TSER/TSIG
TCHCLK
TCHBLK
TSYNC
TSYNC
TCLK
TESO
1
2
t D2
t
D1
t D2
t SU
t D2
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t SU
t
HD
t HD
t
CL
t
CP
t
CH

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