DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 20

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

TSSYNCIO
TSYSCLK
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TCLK1
TCLK2
TCLK3
TCLK4
NAME
TSIG1
TSIG2
TSIG3
TSIG4
CLK1
CLK2
CLK3
CLK4
N13
PIN
P13
C5
D7
M6
M7
D5
R6
C7
P5
B4
F7
A6
T4
A5
P7
L8
L7
TYPE
I/O
I/O
O
I
I
I
Transmit Clock. A 1.544MHz or a 2.048MHz primary clock. Used to clock data
through the transmit side of the transceiver. TSER data is sampled on the falling
edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled
or IBO is not used.
When the elastic store is enabled, TCLKn is used as the internal transmit clock for
the framer side or the elastic store, including the transmit framer and LIU. With the
elastic store enabled, TCLKn can be either synchronous or asynchronous to
TSYSCLKn, which either prevents or allows for slips. In addition, when IBO mode
is enabled, TCLKn must be synchronous to TSYSCLKn, which prevents slips in the
elastic store.
Note: This clock must be provided for proper device operation. The only exception
is when the TCR3 register is configured to source TCLK internally from RCLK.
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz clock. Only used when the transmit-side elastic store function is
enabled. Should be tied low in applications that do not use the transmit-side elastic
store. This is a common clock that is used for the transmitters. The clock can be
4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
Transmit Synchronization. A pulse at these pins establishes either frame or
multiframe boundaries for the transmit side. These signals can also be
programmed to output either a frame or multiframe pulse. If these pins are set to
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signaling frames in T1 mode. The operation of these signals is
synchronous with TCLK.
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for all four transmitters. Should be tied low
in applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26524
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams
can run up to 16.384MHz.
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for per-
channel conditioning.
TCHCLK. TCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, TCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, TCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-to-
serial conversion of channel data. In either mode, TCHCLKn is synchronous with
TCLKn when the receive-side elastic store is disabled or it is synchronous with
TSYSCLKn when the receive-side elastic store is enabled. The mode of TCHCLKn
is determined by the TGCLKEN bit in the TESCR register.
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FUNCTION
DS26524 Quad T1/E1/J1 Transceiver