DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 195

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 7: Transmit Time Slot 0 Pass Through (TTPT).
Bit 6: Transmit Time Slot 16 Data Select (T16S). See Section
Bit 5: Transmit G.802 Enable (TG802). See Section 10.4.
Bit 4: Transmit International Bit Select (TSiS).
Bit 3: Transmit-Signaling All Ones (TSA1).
Bit 2: Transmit HDB3 Enable (THDB3).
Bit 1: Transmit AIS (TAIS).
Bit 0: Transmit CRC-4 Enable (TCRC4).
0 = FAS bits/Sa bits/remote alarm sourced internally from the
1 = FAS bits/Sa bits/remote alarm sourced from TSER
0 = time slot 16 determined by the SSIEx and
1 = source time slot 16 from TS1:TS16 registers
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
0 = sample Si bits at TSER pin
1 = source Si bits from
0 = normal operation
1 = force time slot 16 in every frame to all ones
0 = HDB3 disabled
1 = HDB3 enabled
0 = transmit data normally
1 = transmit an unframed all-ones code at TPOS and TNEG
0 = CRC-4 disabled
1 = CRC-4 enabled
TCR1
TTPT
for T1 mode.
7
0
TCR1 (E1 Mode)
Transmit Control Register 1
181h + (200h x n): where n = 0 to 3, for Ports 1 to 4
T16S
6
0
E1TAF
and
TG802
5
0
E1TNAF
195 of 273
registers (in this mode, TCR1.7 must be set to 0)
TSiS
THSCS1:THSCS4
0
4
8.9.4
TSA1
3
0
E1TAF
on software signaling.
registers
and
THDB3
2
0
E1TNAF
registers
TAIS
1
0
TCRC4
0
0

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