DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 128
DS26524GA4
Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26524GA4.pdf
(273 pages)
Specifications of DS26524GA4
Part # Aliases
90-26524-GA4
- Current page: 128 of 273
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Setting any of the CH[1:24] bits in the T1RSAOI1:T1RSAOI3 registers will cause signaling data to be replaced with
logic ones as reported on RSER. The RSIG signal will continue to report received signaling data. Note that this
feature must be enabled with control bit RSIGC.4.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Digital Milliwatt Enable for Channels 1 to 24 (CH[1:24]).
0 =do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with digital milliwatt code
(MSB) 7
(MSB) 7
CH16
CH24
CH16
CH24
CH8
CH8
0
0
CH15
CH23
CH15
CH23
CH7
CH7
T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only)
Receive-Signaling All-Ones Insertion Registers 1 to 3
038h, 039h, 03Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
T1RDMWE1, T1RDMWE2, T1RDMWE3 (T1 Mode Only)
T1 Receive Digital Milliwatt Enable Registers 1 to 3
03Ch, 03Dh, 03Eh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
6
0
CH14
CH22
CH14
CH22
CH6
CH6
5
0
5
0
CH13
CH21
CH13
CH21
CH5
CH5
4
0
4
0
128 of 273
CH12
CH20
CH12
CH20
CH4
CH4
3
0
3
0
CH11
CH19
CH11
CH19
CH3
CH3
2
0
2
0
CH10
CH18
CH10
CH18
CH2
CH2
1
0
1
0
0 (LSB)
0 (LSB)
CH17
CH17
CH1
CH9
CH1
CH9
0
0
T1RSAOI1
T1RSAOI2
T1RSAOI3
T1RDMWE1
T1RDMWE2
T1RDMWE3
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