DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 22

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

RCHBLK/
RCHBLK/
RCHBLK/
RCHBLK/
BPCLK
NAME
CLK1
CLK2
CLK3
CLK4
WRB/
RDB/
RWB
CSB
DSB
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
C10
PIN
B10
A10
C8
C9
D9
N9
M9
R8
N8
M8
R7
E4
B5
T5
E8
A8
B8
F8
B9
A9
E9
F9
T9
T8
P8
T7
L6
L9
TYPE
O
O
I
I
I
I
I
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-to-
serial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
Address [12:0]. This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
MICROPROCESSOR INTERFACE
22 of 273
FUNCTION
DS26524 Quad T1/E1/J1 Transceiver