DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 159

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is
deleted.
Bit 6: Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a
frame is repeated.
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either
repeated or deleted a frame.
Bit 3: Receive-Signaling Change-of-State Event (RSCOS). Set when any channel selected by the Receive-
Signaling Change-of-State Interrupt Enable registers (RSCSE1:RSCSE3) changes signaling state.
Bit 2: One-Second Timer (1SEC). Set on every one-second interval based on RCLK.
Bit 1: Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated
and are available to be read by the host. The error counter update interval as determined by the settings in the
Error Counter Configuration register (ERCNT).
Bit 0: Receive Multiframe Event (RMF).
T1 Mode: Set on increments of one second or 42ms based on RCLK, or a manual latch event.
E1 Mode: Set on increments of one second or 62.5ms based on RCLK, or a manual latch event.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is
available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
RESF
7
0
RLS4
Receive Latched Status Register 4
093h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RESEM
6
0
RSLIP
5
0
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0
4
RSCOS
3
0
1SEC
2
0
TIMER
1
0
RMF
0
0