DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 246

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DS26524GA4

Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26524GA4

Part # Aliases
90-26524-GA4
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
TSYSCLK
TSYSCLK
TCHBLK
TCHBLK
TCHCLK
TSSYNC
TCHCLK
TSYNC
TSER
TSER
TSIG
1
1
2
2
NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
NOTE 1: TSYNC IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
CHANNEL 23
CHANNEL 31
A
CHANNEL 31
B
LSB MSB
C
LSB MSB
D
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CHANNEL 24
CHANNEL 32
A
CHANNEL 32
B
LSB
C
LSB MSB
F MSB
D
CHANNEL 1
CHANNEL 1
CHANNEL 1

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