DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 134
![no-image](/images/no-image-200.jpg)
DS26524GA4
Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26524GA4.pdf
(273 pages)
Specifications of DS26524GA4
Part # Aliases
90-26524-GA4
- Current page: 134 of 273
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: BOC Bit 5 (RBOC5).
Bit 4: BOC Bit 4 (RBOC4).
Bit 3: BOC Bit 3 (RBOC3).
Bit 2: BOC Bit 2 (RBOC2).
Bit 1: BOC Bit 1 (RBOC1).
Bit 0: BOC Bit 0 (RBOC0).
The T1RBOC register always contains the last valid BOC received. The Receive FDL register (T1RFDL) reports
the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL
updates on multiframe boundaries and reports the six Fs bits in RFDL[5:0].
—
7
0
T1RBOC (T1 Mode)
Receive BOC Register
063h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
6
0
RBOC5
5
0
134 of 273
RBOC4
4
0
RBOC3
3
0
RBOC2
2
0
RBOC1
1
0
RBOC0
0
0
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