DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 167

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For T1 mode, see RIM3.
Bit 7: Loss of Receive Clock Clear (LORCC).
Bit 5: V5.2 Link Detected Clear (V52LNKC).
Bit 4: Receive Distant MF Alarm Clear (RDMAC).
Bit 3: Loss of Receive Clock Detect (LORCD).
Bit 1: V5.2 Link Detect (V52LNKD).
Bit 0: Receive Distant MF Alarm Detect (RDMAD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
LORCC
7
0
RIM3 (E1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
6
0
V52LNKC
5
0
RDMAC
167 of 273
0
4
LORCD
3
0
—
2
0
V52LNKD
1
0
RDMAD
0
0