DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 74

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

8.11.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIP and RRING pins of the DS26524. The user has the option to use internal termination,
software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data from the analog signal and passes it through the jitter attenuation mux. The DS26524 contains an active filter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to
-43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km
(E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the
waveshaping circuitry and line driver. The DS26524 drives the E1 or T1 line from the TTIP and TRING pins via a
coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in
Table 8-35. Registers Related to Control of DS26524 LIU
Global Transceiver Control Register 2
(GTCR2)
Global Transceiver Clock Control Register
(GTCCR)
Global LIU Software Reset Register
(GLSRR)
Global LIU Interrupt Status Register
(GLISR)
Global LIU Interrupt Mask Register
(GLIMR)
LIU Transmit Receive Control Register
(LTRCR)
LIU Transmit Impedance and Pulse Shape
Selection Register (LTITSR)
LIU Maintenance Control Register (LMCR)
LIU Real Status Register (LRSR)
LIU Status Interrupt Mask Register
(LSIMR)
LIU Latched Status Register (LLSR)
LIU Receive Signal Level Register (LRSL)
LIU Receive Impedance and Sensitivity
Monitor Register (LRISMR)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
REGISTER
ADDRESSES
FRAMER
74 of 273
1000h
1001h
1002h
1003h
1004h
1005h
1006h
1007h
0FBh
0FEh
0F2h
0F3h
0F5h
Global transceiver control.
MPS selections, backplane clock
selections
Software reset control for the LIU.
Interrupt status bit for each of the 4 LIUs.
Interrupt mask register for the LIU.
T1/J1/E1 selection, output tri-state, loss
criteria.
Transmit pulse shape and impedance
selection.
Transmit maintenance and jitter
attenuation control register.
LIU real-time status register.
LIU mask registers based on latched
status bits.
LIU latched status bits related to loss, open
circuit, etc.
LIU receive signal level indicator.
LIU impedance match and sensitivity
monitor.
FUNCTION
Table
8-35.