DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 201

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3: Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame
mode only.
Bits 2: Transmit AIS Mode (TAISM). Determines the pattern sent when TAIS (TCR1.1) is activated.
Bits 1 and 0: Transmit Code Length Definition Bits (TC[1:0]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 and 0: Transmit HDLC FIFO Low Watermark Select (TFLWM[1:2]).
TFLWM1
TC1
0
0
1
1
0
0
1
1
0 = transmit normal RAI upon activation with TCR1.0
1 = transmit RAI-CI (T1.403) upon activation with TCR1.0
0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1
1 = transmit AIS-CI (T1.403) upon activation with TCR1.1
TFLWM2
—
—
7
0
7
0
TC0
0
1
0
1
0
1
0
1
TCR4 (T1 Mode Only)
Transmit Control Register 4
186h + (200h x n): where n = 0 to 3, for Ports 1 to 4
THFC
Transmit HDLC FIFO Control Register
187h + (200h x n): where n = 0 to 3, for Ports 1 to 4
TRANSMIT FIFO WATERMARK
—
—
6
0
6
0
LENGTH SELECTED
16 : 8 : 4 : 2 : 1
(BYTES)
(BITS)
6 : 3
—
—
16
32
48
5
0
5
0
5
7
4
201 of 273
—
—
0
0
4
4
TRAIM
—
3
0
3
0
TAISM
—
2
0
2
0
TFLWM1
TC1
1
0
1
0
TFLWM2
TC0
0
0
0
0