PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 211
PCM18XK1
Manufacturer Part Number
PCM18XK1
Description
MODULE PROC PIC18F8680,6680,8565
Manufacturer
Microchip Technology
Datasheet
1.PCM18XK1.pdf
(496 pages)
Specifications of PCM18XK1
Accessory Type
Processor Module
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
ICE2000
For Use With
ICE2000 - EMULATOR MPLAB-ICE 2000 POD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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17.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
FIGURE 17-12:
2004 Microchip Technology Inc.
WR
SSPCON
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
the CKP bit
Clock Synchronization and
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
PIC18F6585/8585/6680/8680
until an external I
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 17-12).
Master device
deasserts clock
2
C master device has already
DS30491C-page 209
DX-1
2
C
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