PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 224

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
17.4.12
An Acknowledge sequence is enabled by setting
the Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
FIGURE 17-24:
DS30491C-page 222
Note: T
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
SCL
SDA
WCOL Status Flag
Write to SSPCON2,
SSPIF
BRG
BRG
Falling edge of
9th clock
Acknowledge sequence starts here,
SDA
Sequence
SCL
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
Set SSPIF at the end
of receive
set PEN
BRG
ACKEN = 1, ACKDT = 0
Enable
. The SCL pin is then
write to SSPCON2
SDA asserted low before rising edge of clock
to setup Stop condition
T
T
BRG
BRG
bit,
8
D0
ACKEN
T
SCL brought high after T
BRG
BRG
)
Cleared in
software
P
T
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
BRG
T
BRG
ACK
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 17-24).
17.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
PEN bit (SSPCON2<2>) is cleared by
T
hardware and the SSPIF bit is set
BRG
9
BRG
BRG
(Baud Rate Generator rollover count) later, the
Set SSPIF at the end
of Acknowledge sequence
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
later, the PEN bit is cleared and the SSPIF
WCOL Status Flag
ACKEN automatically cleared
 2004 Microchip Technology Inc.
Cleared in
software
BRG