STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 25

• Manufacturer Part Number: STEVAL-IFS006V1
• Description: BOARD EVAL 8BIT MICRO + TDE1708
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS006V1

• Design Resources: STEVAL-IFS006V1 Bill of Material
• Sensor Type: Proximity
• Interface: I²C
• Voltage - Supply: 6 V ~ 48 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST7FLITEUS5, TDE1708
• Processor To Be Evaluated: ST7LITEUS5
• Data Bus Width: 8 bit
• Operating Supply Voltage: 6 V to 48 V
• Silicon Manufacturer: ST Micro
• Silicon Core Number: TDE1708DFT
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Proximity Switch
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6403; STEVAL-IFS006V1

ST7LITEUS2, ST7LITEUS5
Bit 7:5 Set to ‘1’
Bit 0 = C Carry/borrow
Bit 4 H Half carry
Bit 3 I Interrupt mask
Bit 2 N Negative
Bit 1 Z Zero
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and
JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Central processing unit
th
bit of the result.
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