STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 51

• Manufacturer Part Number: STEVAL-IFS006V1
• Description: BOARD EVAL 8BIT MICRO + TDE1708
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS006V1

• Design Resources: STEVAL-IFS006V1 Bill of Material
• Sensor Type: Proximity
• Interface: I²C
• Voltage - Supply: 6 V ~ 48 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST7FLITEUS5, TDE1708
• Processor To Be Evaluated: ST7LITEUS5
• Data Bus Width: 8 bit
• Operating Supply Voltage: 6 V to 48 V
• Silicon Manufacturer: ST Micro
• Silicon Core Number: TDE1708DFT
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Proximity Switch
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6403; STEVAL-IFS006V1

ST7LITEUS2, ST7LITEUS5
8.4.1
Caution:
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a
reset.
●
●
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 21. Active-halt timing overview
When exiting Active-halt mode by means of a reset, a 64 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation by fetching the reset vector which woke
it up (see
When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see
Figure
22).
[Active-halt Enabled]
INSTRUCTION
Run
HALT
Active
halt
CYCLE DELAY
INTERRUPT
64 CPU
RESET
OR
1)
VECTOR
FETCH
Run
Power saving modes
Figure
22).
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