STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 64

• Manufacturer Part Number: STEVAL-IFS006V1
• Description: BOARD EVAL 8BIT MICRO + TDE1708
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS006V1

• Design Resources: STEVAL-IFS006V1 Bill of Material
• Sensor Type: Proximity
• Interface: I²C
• Voltage - Supply: 6 V ~ 48 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST7FLITEUS5, TDE1708
• Processor To Be Evaluated: ST7LITEUS5
• Data Bus Width: 8 bit
• Operating Supply Voltage: 6 V to 48 V
• Silicon Manufacturer: ST Micro
• Silicon Core Number: TDE1708DFT
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Proximity Switch
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6403; STEVAL-IFS006V1

I/O ports
9.6
64/136
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 29. Interrupt I/O port state transitions
The I/O port register configurations are summarized in
Table 22.
After reset, to configure PA3 as a general purpose output, the application has to program
the MUXCR0 and MUXCR1 registers. See
Table 23.
0000h
0001h
0002h
Address
(Hex.)
Port A
Port
PADR
Reset
value
PADDR
Reset
value
PAOR
Reset
value
Register
Port configuration
I/O port register map and reset values
label
PA0:2,
PA4:5
PA3
Pin name
floating/pull-up
MSB
MSB
MSB
interrupt
INPUT
7
0
0
0
01
floating
OR = 0
(reset state)
floating
6
0
0
0
INPUT
-
00
Input (DDR=0)
5
0
0
0
open-drain
Section 6.5: Register description on page 37
OUTPUT
pull-up interrupt
10
XX
OR = 1
= DDR, OR
-
4
0
0
0
OUTPUT
push-pull
Table
11
3
0
1
0
22.
open drain
open drain
ST7LITEUS2, ST7LITEUS5
OR = 0
Output (DDR=1)
2
0
0
0
1
0
0
1
push-pull
push-pull
OR = 1
Figure
LSB
LSB
LSB
0
0
0
0
29.