AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet
AT91RM3400-DK
Specifications of AT91RM3400-DK
Related parts for AT91RM3400-DK
AT91RM3400-DK Summary of contents
Page 1
... Required Power Supplies: – 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL – 1.65V to 3.6V on VDDIO • Fully Static Operation MHz @2.7V/1.8V MIPS • Available in a 100-lead LQFP Package ® ® Thumb Processor ™ ARM7TDMI - based Microcontroller AT91RM3400 1790A–ATARM–11/03 1 ...
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... Description AT91RM3400 2 The AT91RM3400 is a fully integrated member of the Atmel advanced AT91 ARM microcontroller family. Having no external memory interface and equipped with embed- ded SRAM and ROM ideal for numerous applications with medium memory requirements but which demand high performance. Several options are available to download software to the internal SRAM. These include downloading from a serial EEPROM or serial DataFlash USB Device Port ...
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... Block Diagram Figure 1. AT91RM3400 Block Diagram Reset TST and NRST Test JTAGSEL TDI JTAG TDO TMS Scan TCK FIQ IRQ0-IRQ6 PCK0-PCK3 PLLRCB PLLB PLLRCA PLLA XIN OSC XOUT XIN32 OSC XOUT32 DRXD DTXD DM DP MCCK MCCDA MCDA0-MCDA3 MCCDB MCDB0-MCDB3 RXD0 TXD0 ...
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... Key Features ARM7TDMI Processor Debug and Test Boot ROM Program Embedded Software Services Reset Controller Memory Controller AT91RM3400 4 • ARM7TDMI Based on ARMv4T Architecture • Two Instruction Sets ® – ARM High-performance 32-bit Instruction Set ® – Thumb High Code Density 16-bit Instruction Set • ...
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... Interrupt Vector Register Reads the Corresponding Current Interrupt Vector • Protect Mode – Easy Debugging by Preventing Automatic Operations when Protect ModeIs Are Enabled • Fast Forcing – Permits Redirecting any Normal Interrupt Source on the Fast Interrupt of the Processor • General Interrupt Mask AT91RM3400 ® Processor 5 ...
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... Power Management Controller System Timer Real-time Clock Debug Unit AT91RM3400 6 – Provides Processor Synchronization on Events Without Triggering an Interrupt • Optimizes the Power Consumption of the Whole System • Embeds and Controls – One Main Oscillator and One Slow Clock Oscillator (32.768Hz) – ...
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... Between Clock and Data Per Chip Select – Programmable Delay Between Consecutive Transfers – Selectable Mode Fault Detection • Connection to PDC Channel Capabilities Optimizes Data Transfers – One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support AT91RM3400 7 ...
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... Two-wire Interface USART Serial Synchronous Controller Timer Counter AT91RM3400 8 • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations • Programmable Baud Rate Generator • 9-bit Full-duplex Synchronous or Asynchronous Serial Communications – ...
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... Minimizes processor intervention for large buffer transfers • USB V2.0 Full-speed Compliant, 12 Mbits per second • Embedded USB V2.0 Full-speed Transceiver • Embedded Dual-port RAM for Endpoints • Suspend/Resume Logic • Ping-pong Mode (2 Memory Banks) for Isochronous and Bulk Endpoints AT91RM3400 9 ...
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... AT91RM3400 10 1790A–ATARM–11/03 ...
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... AT91RM3400 Product Properties Power Supplies The AT91RM3400 has four types of power supply pins: • VDDCORE pins power the chip core and must be between 1.65V and 1.95V, 1.8V nominal. • VDDIO pins power the I/O lines and must be between 1.65V and 3.6V, 1.8V 3.3V nominal. • ...
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... Mechanical Figure 2 shows the orientation of the 100-lead LQFP package. Overview of the A detailed mechanical description is given in the section Mechanical Characteristics of the 100-lead LQFP product datasheet. Package Figure 2. 100-lead LQFP Pinout (Top View) AT91RM3400 100 1790A–ATARM–11/03 ...
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... Peripheral The AT91RM3400 features two PIO controllers (PIOA and PIOB) that allow multiplexing of the I/O lines of the peripheral set. Multiplexing on Each PIO controller controls lines. Each line can be assigned to one of the two PIO Lines peripheral functions The tables in the following paragraphs define how the I/O lines of the peripheral A and B are multiplexed on the PIO controllers A and B. The two columns “ ...
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... Table 2. Multiplexing on PIO Controller A (Continued) PIO Controller A I/O Line Peripheral A PA26 MCDA0 PA27 MCDA1 PA28 MCDA2 PA29 MCDA3 PA30 DRXD PA31 DTXD AT91RM3400 14 Peripheral B Function – RTS2 CTS2 – – Application Usage Comments 1790A–ATARM–11/03 ...
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... IRQ5 PB30 IRQ6 1790A–ATARM–11/03 Peripheral B Function TIOB3 TCLK3 RTS2 RTS3 PCK0 TIOA3 TIOB4 TCLK4 NPCS1 NPCS2 PCK1 TIOA4 TIOB5 TCLK5 NPCS3 PCK1 PCK2 TIOA5 MCCDB MCDB0 DTR1 PCK3 TD0 TD1 TD2 DTXD MCDB1 MCDB2 MCDB3 AT91RM3400 Application Usage Comments 15 ...
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... JTAG Selection NRST Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ6 Interrupt Inputs FIQ Fast Interrupt Input AT91RM3400 16 Type Power Power Power Power Power Ground Ground Ground Clock Generation and Power Management (PMC) Input ...
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... I/O I/O I/O USART I/O I/O Input Output Input Input Output Input Input USB Device Port Analog Analog Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O AT91RM3400 Active Level Comments Pulled-up input at reset Pulled-up input at reset 17 ...
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... Function MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 - NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock AT91RM3400 18 Type Active Level SPI I/O I/O I/O I/O Low Two-wire Interface I/O I/O Comments 1790A– ...
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... Peripheral The AT91RM3400 embeds a wide range of peripherals. Table 5 defines the Peripherals Iden- tifiers of the AT91RM3400. A peripheral identifier is required for the control of the peripheral Identifiers interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. ...
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... Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. Internal ROM The AT91RM3400 features one bank of 256K bytes of ROM. At any time, the ROM is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset and before the Remap Command. ...
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... FCFF System Timer ST 0xFFFF FDFF RTC Real Time Clock 0xFFFF FEFF MC Memory Controller 0xFFFF FFFF AT91RM3400 Size 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers 256 Bytes/64 registers 256 Bytes/64 registers 256 Bytes/64 registers 256 Bytes/64 registers ...
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... User Peripherals Each User Peripheral is allocated 16K bytes of address space. Mapping Figure 5. User Peripherals Mapping AT91RM3400 22 0xF000 0000 Reserved 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 TC3, TC4, TC5 0xFFFA 7FFF 0xFFFA 8000 Reserved 0xFFFA FFFF 0xFFFB 0000 UDP ...
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... The USART section describes features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91RM3400, only the USART1 implements these signals, named DTR1, DSR1, DCD1 and RI1. The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in these USARTs for other features ...
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... AT91RM3400 24 1790A–ATARM–11/03 ...
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... Two Instruction Sets – – • Three-Stage Pipeline Architecture – – – 1790A–ATARM–11/03 ® ARM High-performance 32-bit Instruction Set ® Thumb High Code Density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E) AT91RM3400 ® ® and 16-bit Thumb instruction sets, 25 ...
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... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer AT91RM3400 26 1790A–ATARM–11/03 ...
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... R10 R10 R10 R11 R11 R11 R12 R12 R12 R13_SVC R13_ABORT R13_UNDEF R14_SVC R14_ABORT R14_UNDEF CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF AT91RM3400 Fast Interrupt Interrupt Mode Mode R8_FIQ R9 R9_FIQ R10 R10_FIQ R11 R11_FIQ R12 R12_FIQ R13_IRQ R13_FIQ R14_IRQ R14_FIQ PC PC CPSR ...
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... Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 8 gives the ARM instruction mnemonic list. AT91RM3400 28 supports five types of exception and a privileged processing mode for each 1790A–ATARM–11/03 ...
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... Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor AT91RM3400 Mnemonic Operation CDP Coprocessor Data Processing MVN Move Not ADC Add with Carry SBC ...
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... SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH AT91RM3400 30 Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word ...
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... AT91RM3400 Debug and Test Features Overview 1790A–ATARM–11/03 The AT91RM3400 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit pro- vides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
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... Block Diagram Figure 6. AT91RM3400 Debug and Test Block Diagram Boundary TAP ARM7TDMI PDC Note: TAP: Test Access Port AT91RM3400 32 ICE/JTAG TAP Reset ICE and Test DBGU TMS TCK TDI JTAGSEL TDO NRST TST DTXD DRXD 1790A–ATARM–11/03 ...
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... Debug Environment Test Environment 1790A–ATARM–11/03 Figure 7 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 7. AT91RM3400-based Application Debug Environment Example ICE/JTAG Interface ICE/JTAG Connector AT91RM3400 AT91RM3400-based Application Board Figure 8 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “ ...
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... Debug and Test Pin Description Functional Description Test Pin Embedded In-circuit Emulator AT91RM3400 34 Table 10. Debug and Test Pin List Pin Name Function NRST Microcontroller Reset TST Test Mode Select TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select ...
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... A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. and associated control signals. Each AT91RM3400 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad ...
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... AT91RM3400 36 Table 11. JTAG Boundary Scan Register (Continued) Bit Number Pin Name 183 182 PB20/TXD3/DTR1 181 180 179 PB21/RXD3 178 177 176 PB22/SCK3/PCK3 175 174 173 PB23/FIQ 172 171 170 PB24/IRQ0/TD0 169 168 167 PB25/IRQ1/TD1 166 165 164 PB26/IRQ2/TD2 163 162 161 ...
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... PA6/NPCS3/SCK2 130 129 128 PA7/TWD/PCK2 127 126 125 PA8/TWCK/PCK3 124 123 122 PA9/TXD0 121 120 119 PA10/RXD0 118 AT91RM3400 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL ...
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... AT91RM3400 38 Table 11. JTAG Boundary Scan Register (Continued) Bit Number Pin Name 117 116 PA11/SCK0/TCLK0 115 114 113 PA12/CTS0/TCLK1 112 111 110 PA13/RTS0/TCLK2 109 108 107 PA14/RXD1 106 105 104 PA15/TXD1 103 102 101 PA16/RTS1/TIOA0 100 99 98 PA17/CTS1/TIOB0 PA18/DTR1/TIOA1 PA19/DSR1/TIOB1 PA20/DCD1/TIOA2 88 87 ...
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... PA25/MCCDA/RTS1 PA26/MCDA0 PA27/MCDA1 PA28/MCDA2/RTS2 PA29/MCDA3/CTS2 PA30/DRXD PA31/DTXD PB0/TF0/TIOB3 52 AT91RM3400 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT ...
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... AT91RM3400 40 Table 11. JTAG Boundary Scan Register (Continued) Bit Number Pin Name 51 50 PB1/TK0/TCLK3 PB2/TD0/RTS2 PB3/RD0/RTS3 PB4/RK0/PCK0 PB5/RF0/TIOA3 PB6/TF1/TIOB4 PB7/TK1/TCLK4 PB8/TD1/NPCS1 PB9/RD1/NPCS2 PB10/RK1/PCK1 PB11/RF1/TIOA4 19 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT ...
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... Bit Number Pin Name 18 17 PB12/TF2/TIOB5 PB13/TK2/TCLK5 PB14/TD2/NPCS3 PB15/RD2/PCK1 PB16/RK2/PCK2 PB17/RF2/TIOA5 1 AT91RM3400 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL ...
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... VERSION PART NUMBER 7 6 VERSION: Product Version Number Set to 0x1. PART NUMBER: Product Part Number Set to 0x5B03. MANUFACTURER IDENTITY Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91RM3400 JTAG ID Code value is 0x15B0303F. AT91RM3400 PART NUMBER MANUFACTURER IDENTITY 26 25 PART NUMBER ...
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... Boot Uploader in case no valid program is detected in external NVM and supporting several communication media • Serial communication on a DBGU (XModem protocol) • USB Device Port (DFU Protocol) 1790A–ATARM–11/03 ® SPI DataFlash connected on SPI NPCS0 Two-wire EEPROM 8-bit parallel memories on NCS0 (only for devices with EBI integrated) AT91RM3400 43 ...
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... Device Setup SPI DataFlash Boot Timeout 10 ms TWI EEPROM Boot Timeout 40 ms Parallel Boot Applicable only to parallel boot interfaces OR *DFU = Device Firmware Upgrade AT91RM3400 44 Yes Download from DataFlash Download from Yes EEPROM Yes Download from 8-bit Device DBGU Serial Download USB Download ...
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... LDR PC,[PC,20] e59ff014 LDR PC,[PC,20] e59ff014 LDR PC,[PC,20] e59ff014 LDR PC,[PC,20] 00001234 LDR PC,[PC,20] e51fff20 LDR PC,[PC,-0xf20] e51fff20 LDR PC,[PC,-0xf20] AT91RM3400 Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 00 ea00000b B 0x2c 04 e59ff014 LDR PC,[PC,20] 08 e59ff014 LDR PC,[PC,20] 0c e59ff014 LDR ...
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... An example of valid vectors: 00 004 download mode (DataFlash, EEPROM or 8-bit memory in device with EBI integrated), the size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. AT91RM3400 ...
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... Number of Reserved Pages (Nb of pages) DataFlash page number = 2 Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 128 Mbits AT91RM3400 Number of 512-byte Blocks to Download Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 528 4096 ...
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... DataFlash connected to the NPCS0 of the SPI, followed by the serial EEPROM con- nected to the TWI and by an 8-bit parallel memory connected on NCS0 of the External Bus Interface (if EBI is implemented in the product). AT91RM3400 48 PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB ...
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... LDR or Branch instruction ? Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91RM3400 No Serial Two-Wire EEPROM Download No 49 ...
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... Generally, serial EEPROMs have no identification code. The bootloader checks for an EEPROM Download acknowledgment on the first read. The device address on the two-wire bus must be 0x0. The bootloader supports the devices listed in Table 14. Table 14. Supported EEPROM Devices Figure 15. Serial Two-Wire EEPROM Download AT91RM3400 50 Device AT24C16A 16 Kbits AT24C164 ...
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... No (except vector 6) are LDR or Branch instruction ? Yes Read the external memory into the internal SRAM (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91RM3400 Memory uploader 51 ...
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... Figure 17 shows a transmission using this protocol. AT91RM3400 52 Initialization of the DBGU serial port (115200 bauds and Xmodem protocol start Initialization of the USB Device Port and DFU protocol start Download of the application < ...
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... SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Host Prepare for an upgrade USB reset DFU mode activated Download this firmware Prepare to exit DFU mode USB reset AT91RM3400 Device Device 53 ...
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... Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the Boot Program are set to their reset state. Table 15. Pins Driven during Boot Program Execution Pin Used MOSI SPCK NPCS0 TWD TWCK Note: AT91RM3400 54 SPI (Dataflash) (1) (1) (1) (1) (1) 1. See “Peripheral Multiplexing on PIO Lines” on page 13. TWI (EEPROM) ...
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... AT91F_Open_<Service> the only entry point defined for a service. Even if the functions AT91F_Open_<Service> may be compared with object constructors, they do not act as constructors in that they initiate the service structure but they do not allocate it. Thus the customer application must allocate it. Example 1790A–ATARM–11/03 AT91RM3400 55 ...
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... It is possible to overload just one method of a service or all the methods of a service. In this latter case, the functionality of the service is user-defined, but still works on the same data structure. Note: AT91RM3400 56 Calling the default function AT91F_Open_<Service> ensures that all methods and data are initialized. ...
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... Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Overloading Open Service Method AT91PS_Service My_OpenService( AT91PS_Service pService) { AT91F_OpenService(pService); // Overloading ChildMethod default value pService->ChildMethod= My_ChildMethod; return pService Allocation of the service structure AT91S_Service service; // Opening of the service AT91PS_Service pService = My_OpenService(&service); AT91RM3400 57 ...
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... Init the service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) { pService->data = 0; pService->MainMethod =AT91F_MainMethod; pService->ChildMethod=AT91F_ChildMethod; return pService; } AT91RM3400 58 method: Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Allocation of the service structure AT91S_Service service; // Opening of the service AT91PS_Service pService = AT91F_OpenService(& ...
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... ROM Memory Space AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtlTempo, void const *pTempoTimer ) { ... } AT91S_TempoStatus AT91F_CtlTempoCreate ( AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) { ... } structure. To obtain the Open Service Method of another service stored in can be found at the beginning of the ROM, after the AT91S_RomBoot AT91RM3400 function), they must . Some members AT91S_RomBoot structure. AT91S_RomBoot 59 ...
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... AT91PS_CtlTempo pCtrl) // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoCreate(...); // Default Method: AT91S_TempoStatus AT91F_CtlTempoCreate ( AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) AT91RM3400 60 Description Member of AT91S_RomBoot structure. Corresponds to the Open Service Method for the Tempo Service. Input Parameters: Pointer on a Control Tempo Object. Pointer on a System Timer Descriptor Structure. ...
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... Number of times to reload the tempo after timeout completed for periodic execution. Callback on a method to launch once the timeout completed. Allows to have a hook on the current service. Output Parameters: Returns 1. Member of structure. AT91S_SvcTempo Force to stop a software timer. Input Parameters: Pointer on a Service Tempo Object. Output Parameters: Returns 1. AT91RM3400 61 ...
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... AT91S_SvcTempo svcTempo2; • Initializes the AT91S_SvcTempo object calling the AT91F_CtlTempoCreate method of the AT91S_CtlTempo service: // Init the svcTempo2, link it to the AT91S_CtlTempo object ctlTempo.CtlTempoCreate(&ctlTempo, &svcTempo2); AT91RM3400 62 ) method replaced by the applica- &ctlTempo, &svcTempo1 method of the svcTempo1 object. Depending on the function Start 1790A–ATARM–11/03 ...
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... AT91S_PipeStatus (*AbortWrite) (struct _AT91S_Pipe AT91S_PipeStatus (*AbortRead) (struct _AT91S_Pipe *pPipe); AT91S_PipeStatus (*Reset) (struct _AT91S_Pipe *pPipe); char (*IsWritten) (struct _AT91S_Pipe *pPipe,char const *pVoid); char (*IsReceived) (struct _AT91S_Pipe *pPipe,char const *pVoid); AT91RM3400 AT91PS_SvcComm AT91PS_Buffer *pPipe); 63 ...
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... Size); *pBuffer, unsigned int Size); **pData, unsigned int *pSize); **pData, unsigned int *pSize); int size); int size); } AT91S_Buffer, *AT91PS_Buffer; AT91RM3400 64 struct _AT91S_Pipe *pPipe; void *pChild; // Functions invoked by the pipe AT91S_BufferStatus (*SetRdBuffer) AT91S_BufferStatus (*SetWrBuffer) AT91S_BufferStatus (*RstRdBuffer) AT91S_BufferStatus (*RstWrBuffer) char (*MsgWritten) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer) ...
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... AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService); char (*TxReady)(struct _AT91S_Service *pService); char (*RxReady)(struct _AT91S_Service *pService); // Data: struct _AT91S_Buffer *pBuffer; // Link to a buffer object void *pChild; AT91RM3400 65 ...
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... Xmodem protocol). This feature is provided by the Tempo Service. The following structure defines the Xmodem Service: typedef struct _AT91PS_SvcXmodem { csr); csr); } AT91S_SvcXmodem, *AT91PS_SvcXmodem AT91RM3400 66 // Public Methods: AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StopTx) (struct _AT91PS_SvcXmodem *, unsigned int) ...
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... Pointer on a CtlTempo structure. Output Parameters: Returns the Xmodem Service Pointer Structure. Member of structure. AT91S_SvcXmodem interrupt handler for xmodem read or write functionnalities Input Parameters: Pointer on a Xmodem Service Structure. csr: usart channel status register . Output Parameters: Status for xmodem read or write. AT91RM3400 67 ...
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... Open PIO for DBGU // Initialize the Interrupt for System Timer and DBGU (shared interrupt) // Initialize the Interrupt Source 1 for SysTimer and DBGU xmodemPipe.Read(&xmodemPipe, (char *) BASE_LOAD_ADDRESS, MEMORY_SIZE, XmodemProtocol, (void *) BASE_LOAD_ADDRESS); AT91RM3400 68 sXmBuffer; // Xmodem Buffer allocation xmodemPipe;// xmodem pipe communication struct ctlTempo; // Tempo struct = pAT91-> ...
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... Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Member of structure AT91S_SvcDataFlash Allows to reset PDC & Interrupts. Input Parameters: Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: None. AT91RM3400 69 ...
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... Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.MainMemoryToBufferTransfert(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_MainMemoryToBufferTransfert( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int page) AT91RM3400 70 Description Member of structure AT91S_SvcDataFlash Read a Page in DataFlash. Input Parameters: Pointer on DataFlash Service Structure. DataFlash address. Data buffer destination pointer. ...
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... Returns 5 if DataFlash Bad Address. Member of structure. AT91S_SvcDataFlash Write Internal Buffer to the DataFlash Main Memory. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer command. Main memory address on DataFlash. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. AT91RM3400 71 ...
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... Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.MainMemoryToBufferCompare(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_MainMemoryToBufferCompare( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int page) Note: AT91S_SvcDataFlashStatus corresponds to an unsigned int. AT91RM3400 72 Description Member of structure. AT91S_SvcDataFlash Erase a page in DataFlash. Input Parameters: Pointer on a Service DataFlash Object. Page to erase. Output Parameters: Returns 0 if DataFlash is Busy ...
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... Now the different methods can be used. Following is an example of a Page Read of 528 bytes on page 50: // Result of the read operation in RxBufferDataFlash unsigned char RxBufferDataFlash[528]; svcDataFlash.PageRead(&svcDataFlash, 1790A–ATARM–11/03 AT91S_SvcDataFlash instance by calling the AT91S_SvcDataFlash : SPI Interrupt AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ,AT91F_spi_asm_handler); service structure: AT91S_SvcDataFlash (50*528),RxBufferDataFlash,528); AT91RM3400 AT91F_OpenSvcDataFlash and in the application AT91S_Dataflash AT91F_OpenSvcDataFlash using 73 ...
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... Typical Use: char reverse_byte; reverse_byte = pAT91->Bit_Reverse_Array[...]; // Array Embedded: const unsigned char bit_rev[256] AT91RM3400 74 AT91S_RomBoot Description This function provides a table driven 32bit CRC generation for byte data. This CRC is known as the CCITT CRC32. Input Parameters: Pointer on the data buffer ...
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... Using the Service Compute the CRC16 CCITT of a 256-byte buffer and save it in the crc16 variable: // Compute CRC16 CCITT unsigned char BufferToCompute[256]; short crc16; ... (BufferToCompute Treatment) pAT91->CRCCCITT(&BufferToCompute,256,&crc16); 1790A–ATARM–11/03 AT91RM3400 75 ...
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... Default Method: short AT91F_Sinus(int step) // Typical Use: short sinus; sinus = pAT91->SineTab[...]; // Array Embedded: const short AT91C_SINUS180_TAB[256] AT91RM3400 76 AT91S_RomBoot Description This function returns the amplitude coded on 16 bits sine waveform for a given step. Input Parameters: Step of the sine. Corresponds to the precision of the amplitude calculation ...
Page 77
... NRST NRST is the active low reset input. When power is first applied to the system, a power-on reset (also called a “cold” reset) must be applied to the AT91RM3400. During this transient state, it Conditions is mandatory to hold the reset signal low long enough for the power supply to reach a working nominal level and for the oscillator to reach a stable operating frequency ...
Page 78
... NRST pin. In fact, the cold reset assertion has to overlap the start-up time of the system. The user reset request requires a smaller assertion delay time than the cold reset. Recommended The following table gives an overview of the recommended features of a reset controller in order to obtain an optimal system with the AT91RM3400 device. Features of the Reset Table 25. Reset Controller Function Overview ...
Page 79
... It features a simple bus arbiter, an address decoder, an abort status and a misalignment detector. In addition, the MC contains a Memory Protection Unit (MPU) consisting of 16 areas that can be protected against write and/or user accesses. Access to peripherals can be protected in the same way. Main features of the AT91RM3400 Memory Controller are: • Bus Arbiter – ...
Page 80
... Block Diagram Figure 21. Memory Controller Block Diagram ARM7TDMI Processor Abort Peripheral Data Controller AT91RM3400 80 Memory Controller Abort Status Address Decoder Misalignment Detector Bus Arbiter Memory Protection Unit User Interface APB Bridge Peripheral 0 APB Peripheral 1 Peripheral N ASB Internal Memories From Master to Slave ...
Page 81
... An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 22 shows the assignment of the 256-Mbyte memory areas. Figure 22. Memory Areas 256M Bytes 14 x 256MBytes 3,584 Mbytes 256M Bytes AT91RM3400 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 Undefined (Abort) 0xEFFF FFFF ...
Page 82
... Internal Memory Mapping Internal Memory Area 0 Remap Command AT91RM3400 82 Within the Internal Memory address space, the Address Decoder of the Memory Con- troller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory ...
Page 83
... Protection Unit Peripheral Register (MC_PUP) with the field PROT at the appropriate value. The peripheral address space and each internal memory area can be protected against write and non-privileged access of one of the masters. When one of the masters per- forms a forbidden access, an Abort is generated and the Abort Status traces what has happened. AT91RM3400 83 ...
Page 84
... Misalignment Detector AT91RM3400 84 There is no priority in the protection of the memory spaces. In case of overlap between several memory spaces, the strongest protection is taken into account access is performed to an address which is not contained in any of the 16 memory spaces, the Memory Protection Unit generates an abort. To prevent this, the user can define a mem- ory space of 4M bytes starting at 0 and authorizing any access ...
Page 85
... AT91RM3400 Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 26. MC Register Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x0C Reserved 0x10 MC Protection Unit Area 0 0x14 MC Protection Unit Area 1 0x18 MC Protection Unit Area 2 ...
Page 86
... RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. AT91RM3400 – – – – – – – ...
Page 87
... Abort Size Byte Half-word Word Reserved Abort Type Data Read Data Write Code Fetch Reserved AT91RM3400 26 25 – SVMST1 18 17 – MST1 10 9 ABTTYP ABTSZ 2 1 MPU MISADD 24 SVMST0 16 MST0 8 0 UNDADD 87 ...
Page 88
... At least one abort due to the ARM7TDMI occurred since the last read of MC_ASR. • SVMST1: Saved PDC Abort Source 0: No abort due to the PDC occurred since the last read of MC_ASR notified in the bit MST1 least one abort due to the PDC occurred since the last read of MC_ASR. AT91RM3400 88 1790A–ATARM–11/03 ...
Page 89
... MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Absolute Address: 0xFFFF FF08 • ABTADD: Abort Address This field contains the address of the last aborted access. 1790A–ATARM–11/ ABTADD ABTADD ABTADD ABTADD AT91RM3400 ...
Page 90
... PROT: Protection : PROT access 0 1 Read/Write 1 0 Read/Write 1 1 Read/Write • SIZE: Internal Area Size : SIZE AT91RM3400 – – Processor Mode Privilege User No access No access Read-only Read/Write Area Size LSB 128 KB 17 256 KB 18 512 – – – – – – 24 – ...
Page 91
... Read/Write 1 0 Read/Write 1 1 Read/Write 1790A–ATARM–11/ – – – – – – – – Processor Mode Privilege User No access No access Read-only Read/Write AT91RM3400 – – – – – – – – – – – 24 – 16 – 8 – 0 PROT 91 ...
Page 92
... Absolute Address: 0xFFFFFF54 31 30 – – – – – – – – • PUEB: Protection Unit Enable Bit 0: The Memory Controller Protection Unit is disabled. 1: The Memory Controller Protection Unit is enabled. AT91RM3400 – – – – – – – – – – ...
Page 93
... One Master Clock Cycle Needed for a Transfer from Memory to Peripheral • Two Master Clock Cycles Needed for a Transfer from Peripheral to Memory Block Diagram Figure 24. Block Diagram 1790A–ATARM–11/03 Peripheral Data Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & Control Control AT91RM3400 Memory Control Controller 93 ...
Page 94
... If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero, AT91RM3400 94 1790A–ATARM–11/03 ...
Page 95
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitters requests. 1790A–ATARM–11/03 AT91RM3400 95 ...
Page 96
... USART, SSC, SPI, MCI etc). PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read/Write • RXPTR: Receive Pointer Address Address of the next receive transfer. AT91RM3400 96 Register Name (1) PERIPH _RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR 29 ...
Page 97
... PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read/Write • TXCTR: Transmit Counter Value ·TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped. 1790A–ATARM–11/ RXCTR RXCTR TXPTR TXPTR TXPTR TXPTR TXCTR TXCTR AT91RM3400 ...
Page 98
... RXNCR: Receive Next Counter Value ·RXNCR is the size of the next buffer to receive. PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read/Write • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. AT91RM3400 RXNPTR RXNPTR RXNPTR ...
Page 99
... Transmitter Transfer Disable effect Disables the transmitter PDC transfer requests 1790A–ATARM–11/ TXNCR TXNCR – – – – – – – – – – – – AT91RM3400 – – – – – – – TXTDIS TXTEN – RXTDIS RXTEN 99 ...
Page 100
... Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • ·TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. AT91RM3400 100 – – – ...
Page 101
... Interrupt Vector Register Reads the Corresponding Current Interrupt Vector Easy Debugging by Preventing Automatic Operations when Protect ModeIs Are Enabled Permits Redirecting any Normal Interrupt Source on the Fast Interrupt of the Processor Provides Processor Synchronization on Events Without Triggering an Interrupt AT91RM3400 ® Processor 101 ...
Page 102
... Block Diagram Figure 25. Block Diagram Application Figure 26. Description of the Application Block Block Diagram AIC Detailed Figure 27. AIC Detailed Block Diagram Block Diagram AT91RM3400 102 FIQ IRQ0-IRQn Embedded PeripheralEE Embedded Peripheral Embedded Peripheral Standalone OS Drivers Applications General OS Interrupt Handler Advanced Interrupt Controller ...
Page 103
... Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 1790A–ATARM–11/03 Pin Description Fast Interrupt Interrupt 0 - Interrupt n AT91RM3400 Type Input Input 103 ...
Page 104
... The AIC_ISR register reads the number of the current interrupt (see “Priority Controller” on page 107) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. AT91RM3400 104 1790A–ATARM–11/03 ...
Page 105
... Source Input Stage Source i 1790A–ATARM–11/03 MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active AIC_SMRi SRCTYPE High/Low Pos./Neg. Edge Detector Set Clear AIC_ISCR AIC_ICCR AT91RM3400 Level/ AIC_IPR Edge AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR 105 ...
Page 106
... The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. External Interrupt Figure 30. External Interrupt Edge Triggered Source Edge Triggered Source External Interrupt Figure 31. External Interrupt Level Sensitive Source Level Sensitive Source AT91RM3400 106 MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles ...
Page 107
... AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 1790A–ATARM–11/03 MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active AT91RM3400 107 ...
Page 108
... When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with AT91RM3400 108 PC,[PC,# -&F20] 1790A–ATARM–11/03 ...
Page 109
... If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. The “I” bit in SPSR is significant set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). AT91RM3400 109 ...
Page 110
... Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR AT91RM3400 110 PC,[PC,# -&F20] ...
Page 111
... Fast Interrupt sources. 1790A–ATARM–11/03 The "F" bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). AT91RM3400 111 ...
Page 112
... Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. AT91RM3400 112 Input Stage Automatic Clear Read FVR if Fast Forcing is disabled on Sources 1 to 31. ...
Page 113
... AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 1790A–ATARM–11/03 AT91RM3400 113 ...
Page 114
... Fast Forcing Disable Register 0x148 Fast Forcing Status Register Note: 1. The reset value of the Interrupt Pending Register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. AT91RM3400 114 Name Access Reset Value AIC_SMR0 Read/Write ...
Page 115
... Internal Interrupt Sources Level Sensitive Edge Triggered Level Sensitive Edge Triggered VECTOR VECTOR VECTOR VECTOR AT91RM3400 – – – – – – – – – PRIOR 115 ...
Page 116
... Reset Value • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the Fast Interrupt Vector Register reads the value stored in AIC_SPU. AT91RM3400 116 IRQV IRQV IRQV ...
Page 117
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91RM3400 – – – – – – – – – IRQID PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 2 ...
Page 118
... Reset Value – – – – – – – – • NFIQ: NFIQ Status 0 = nFIQ line is deactivated nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated nIRQ line is active. AT91RM3400 118 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 ...
Page 119
... PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91RM3400 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ PID26 PID25 PID24 PID18 PID17 PID16 PID10 ...
Page 120
... AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Set effect Sets corresponding interrupt. AT91RM3400 120 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 ...
Page 121
... AIC_FVR in case of a spurious fast interrupt. 1790A–ATARM–11/ – – – – – – – – – – – – SIQV SIQV SIQV SIQV AT91RM3400 – – – – – – – – – – – – 121 ...
Page 122
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. AT91RM3400 122 – – ...
Page 123
... PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91RM3400 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – PID26 PID25 PID24 PID18 PID17 PID16 PID10 ...
Page 124
... PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enable on the corresponding interrupt. AT91RM3400 124 PID29 PID28 PID27 PID21 PID20 PID19 13 12 ...
Page 125
... UDPCK for the USB Device Port – Programmable Automatic PLL Switch-off in USB Device Suspend Conditions – Thirty Peripheral Clocks – Four Programmable Clock Outputs • Four Operating Modes – Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode AT91RM3400 125 ...
Page 126
... Oscillator Clock XOUT PLL and PLLA PLLRCA Divider A Clock PLLB PLL and PLLRCB Clock Divider B User Interface APB AT91RM3400 126 Master Clock Controller SLCK Divider Prescaler Main Clock /1,/2,/3,/4 /2,/4,...,/64 PLLA Clock ARM9-systems PLLB Clock only Peripherals Clock Controller ON/OFF ...
Page 127
... USB Host Port, and the UDPCK for the USB Device. If the product does not embed the USB Host Port or the USB Device Port, the associ- ated control bits and registers are not implemented in the PMC and programming them has no effect on the behavior of the PMC. AT91RM3400 127 ...
Page 128
... Functional Description Operating Modes Definition Clock Definitions Clock Generator AT91RM3400 128 The following operating modes are supported by the PMC and offer different power con- sumption levels and event response latency times: • Normal Mode: The ARM processor clock is enabled and peripheral clocks are enabled depending on application requirements. • ...
Page 129
... However, this startup is only required in case of cold reset, i.e. in case of system power-up. When a warm reset occurs, the length of the reset pulse may be much lower. For further details, see the section “Reset Controller” on page 77. AT91RM3400 Clock Generator Divider A ...
Page 130
... Main Oscillator Main Oscillator Connections Main Oscillator Startup Time Main Oscillator Control AT91RM3400 130 Figure 38 shows the Main Oscillator block diagram. Figure 38. Main Oscillator Block Diagram XIN XOUT Slow Clock The Clock Generator integrates a Main Oscillator that is designed for MHz fun- damental crystal ...
Page 131
... While this bit the pin XIN is tied low to prevent any internal oscillation regardless of pin connected. The external clock signal must meet the requirements relating to the power supply VDDPLL (i.e., between 1.65V and 1.95V) and cannot exceed 50 MHz. AT91RM3400 131 ...
Page 132
... Divider and PLL Blocks PLL Filters AT91RM3400 132 The Clock Generator features two Divider/PLL Blocks that generates a wide range of frequencies. Additionally, they provide a 48 MHz signal to the embedded USB device and/or host ports, regardless of the frequency of the Main Clock. Figure 40 shows the block diagram of the divider and PLL blocks. ...
Page 133
... MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock enables Slow Clock Mode by providing a 32.768 kHz signal to the whole device. Selecting the Main Clock saves power consumption of both PLLs, but AT91RM3400 133 ...
Page 134
... Processor Clock Controller Processor Clock Source Idle Mode AT91RM3400 134 prevents using the USB ports. Selecting the PLLB Clock saves the power consumption of the PLLA by running the processor and the peripheral at 48 MHz required by the USB ports. Selecting the PLLA Clock runs the processor and the peripherals at their maxi- mum speed while running the USB ports at 48 MHz ...
Page 135
... PMC_PCK0 to PMC_PCK3. PCK0 to PCK3 can be independently selected between the four clocks provided by the Clock Generator by writing the CSS field in PMC_PCK0 to PMC_PCK3. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the field PRES (Prescaler) in PMC_PCK0 to PMC_PCK3. AT91RM3400 135 ...
Page 136
... AT91RM3400 136 Each output signal can be enabled and disabled by writing 1 in the corresponding bit PCK0 to PCK3 of PMC_SCER and PMC_SCDR, respectively. Status of the active pro- grammable output clocks are given in the bits PCK0 to PCK3 of PMC_SCSR (System Clock Status Register). Moreover, like the MCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers ...
Page 137
... Main Clock – – 2.5 x PLLA Clock + 5 x SLCK + PLLACOUNT x SLCK 2.5 x PLLB Clock + 5 x SLCK + PLLBCOUNT x SLCK AT91RM3400 PLLA Clock PLLB Clock 3 x PLLA Clock + 3 x PLLB Clock + 4 x SLCK + 4 x SLCK + 1 x Main Clock 1 x Main Clock 3 x PLLA Clock + ...
Page 138
... Figure 43. Switch Master Clock from Slow Clock to PLLA Clock Slow Clock PLLA Clock LOCK A MCKRDY Master Clock Write PMC_MCKR Figure 44. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR AT91RM3400 138 1790A–ATARM–11/03 ...
Page 139
... Figure 45. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Write CKGR_PLLAR Figure 46. Programmable Clock Output Programming PLLA Clock PCKRDY PCKx Output Write PMC_PCKX Write PMC_SCER Write PMC_SCDR 1790A–ATARM–11/03 Slow Clock PLLA Clock is selected PCKx is enabled AT91RM3400 PCKx is disabled 139 ...
Page 140
... Reserved 0x0054 Reserved 0x0058 Reserved 0x005C Reserved 0x0060 Interrupt Enable Register 0x0064 Interrupt Disable Register 0x0068 Status Register 0x006C Interrupt Mask Register AT91RM3400 140 Name Access PMC_SCER Write-only PMC_SCDR Write-only PMC _SCSR Read-only – – PMC _PCER Write-only PMC_PCDR Write-only ...
Page 141
... PCK0...PCK3: Programmable Clock Output Enable effect Enables the corresponding Programmable Clock output. 1790A–ATARM–11/ – – – – – – – – PCK3 – UHP – AT91RM3400 – – – – PCK2 PCK1 PCK0 2 1 MCKUDP UDP PCK – – 141 ...
Page 142
... Disables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs. • UHP: USB Host Port Clock Disable effect Disables the 48 MHz clock of the USB Host Port. • PCK0...PCK3: Programmable Clock Output Disable effect Disables the corresponding Programmable Clock output. AT91RM3400 142 – – ...
Page 143
... The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. 1790A–ATARM–11/ – – – – – – – – PCK3 – UHP – AT91RM3400 – – – – PCK2 PCK1 PCK0 2 1 MCKUDP UDP PCK – – 143 ...
Page 144
... Register Name: PMC_PCDR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PID2...PID31: Peripheral Clock Disable effect Disables the corresponding peripheral clock. AT91RM3400 144 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 145
... PID2...PID31: Peripheral Clock Status 0 = The corresponding peripheral clock is disabled The corresponding peripheral clock is enabled. 1790A–ATARM–11/ PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 AT91RM3400 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 – – 145 ...
Page 146
... The Main Oscillator is disabled. Main Clock is the signal connected on XIN The Main Oscillator is enabled. A crystal must be connected between XIN and XOUT. • OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles for the Main Oscillator start-up time. AT91RM3400 146 – ...
Page 147
... MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. 1790A–ATARM–11/ – – – – – – MAINF MAINF AT91RM3400 – – – – – MAINRDY 147 ...
Page 148
... Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. • OUTA: PLLA Clock Frequency Range OUTA • MULA: PLL A Multiplier 0 = The PLL A is deactivated 2047 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. AT91RM3400 148 – – MULA 13 12 ...
Page 149
... Clock MHz. 1790A–ATARM–11/ – USB_96M – MULB PLLBCOUNT DIVB Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVB. PLLB Clock Frequency Range 80 MHz to 160 MHz Reserved 150 MHz to 240 MHz Reserved AT91RM3400 MULB 149 ...
Page 150
... The Master Clock and the Processor Clock are the same The Processor Clock is twice as fast as the Master Clock The Processor Clock is three times faster than the Master Clock The Processor Clock is four times faster than the Master Clock. AT91RM3400 150 – ...
Page 151
... PRES CSS PRES AT91RM3400 – – – – – – – – – CSS Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 ...
Page 152
... MOSCS: Main Oscillator Status • LOCKA: PLL A Lock • LOCKB: PLL B Lock • MCKRDY: Master Clock Ready • PCK0RDY - PCK3RDY: Programmable Clock Ready effect Disables the corresponding interrupt. AT91RM3400 152 – – – – – – ...
Page 153
... PCK0RDY - PCK3RDY: Programmable Clock Ready Status 0 = Programmable Clock not ready Programmable Clock ready. 1790A–ATARM–11/ – – – – – – – – PCK3RDY – – MCKRDY AT91RM3400 26 25 – – – – PCK2RDY PCK1RDY PCK0RDY 2 1 LOCKB LOCKA MOSCS 24 – 16 – 153 ...
Page 154
... MOSCS: Main Oscillator Status • LOCKA: PLL A Lock • LOCKB: PLL B Lock • MCKRDY: Master Clock Ready • PCK0RDY - PCK3RDY: Programmable Clock Ready • MOSCS: MOSCS Interrupt Mask 0 = The corresponding interrupt is enabled The corresponding interrupt is disabled. AT91RM3400 154 – – – ...
Page 155
... Figure 48. Application Block Diagram Block Diagram 1790A–ATARM–11/03 System Timer APB Periodic Interval Timer Real-Time Timer Power SLCK Management Watchdog Timer Controller STIRQ Advanced Interrupt Controller OS or RTOS Date, Time Scheduler and Alarm Manager PIT RTT AT91RM3400 NWDOVF System Survey Manager WDT 155 ...
Page 156
... Warning: If ST_PIMR is programmed with a period less or equal to the current MCK period, the update of the PITS status bit and its associated interrupt generation are unpredictable. Figure 49. Period Interval Timer AT91RM3400 156 PIV 16-bit ...
Page 157
... TC_SR is set. The alarm register is set to its maximum value, corresponding to 0, after a reset. The bit RTTINC in ST_SR is set each time the 20-bit counter is incremented. This bit can be used to start an interrupt, or generate a one-second signal. 1790A–ATARM–11/03 SLCK 16-bit Down 1/128 Counter WDRST AT91RM3400 WV WDOVF Status RSTEN Internal Reset EXTEN NWDOVF 157 ...
Page 158
... This also resets the 20-bit counter. Warning: If RTPRES is programmed with a period less or equal to the current MCK period, the update of the RTTINC and ALMS status bits and their associated interrupt generation are unpredictable. Figure 51. Real Time Timer AT91RM3400 158 RTPRES SLCK ...
Page 159
... ST_IMR ST_RTAR ST_CRTR – – – – – – – – – – – – AT91RM3400 Access Reset Value Write-only – Read/Write 0x00000000 Read/Write 0x00020000 Read/Write 0x00008000 Read-only – Write-only – Write-only – Write-only 0x0 Read/Write 0x0 Read-only 0x0 – – ...
Page 160
... No reset is generated when a watchdog overflow occurs internal reset is generated when a watchdog overflow occurs. • EXTEN: External Signal Assertion Enable 0 = The watchdog_overflow is not tied low when a watchdog overflow occurs The watchdog_overflow is tied low during 8 slow clock cycles when a watchdog overflow occurs. AT91RM3400 160 – – – ...
Page 161
... RTPRES RTPRES – – – – – – – – – – – ALMS AT91RM3400 – – – – – – – – – – – – – – – RTTINC WDOVF PITS 161 ...
Page 162
... PITS: Period Interval Timer Status Interrupt Disable • WDOVF: Watchdog Overflow Interrupt Disable • RTTINC: Real-time Timer Increment Interrupt Disable • ALMS: Alarm Status Interrupt Disable effect Disables the corresponding interrupt. AT91RM3400 162 – – – – ...
Page 163
... ALMV to 0x0 corresponding to 1048576 seconds. 1790A–ATARM–11/ – – – – – – – – – – – ALMS – – – – – ALMV ALMV AT91RM3400 – – – – – – – – – RTTINC WDOVF PITS – – – ALMV 163 ...
Page 164
... ST Current Real-Time Register Register Name: ST_CRTR Access Type: Read-only 31 30 – – – – • CRTV: Current Real-time Value Returns the current value of the real-time timer. AT91RM3400 164 – – – – – CRTV CRTV – – – CRTV 1790A–ATARM–11/03 ...
Page 165
... This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer, Real Time Clock, Power Management Controller, Memory Controller, etc.). When a 1790A–ATARM–11/03 32768 Divider Time Bus Interface Entry Control AT91RM3400 Date Interrupt RTC Interrupt Control 165 ...
Page 166
... The user can not reset this flag reset as soon as an accept- able value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) AT91RM3400 166 1790A–ATARM–11/03 ...
Page 167
... If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be programmed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. AT91RM3400 167 ...
Page 168
... RTC Status Register 0x1C RTC Status Clear Command Register 0x20 RTC Interrupt Enable Register 0x24 RTC Interrupt Disable Register 0x28 RTC Interrupt Mask Register 0x2C RTC Valid Entry Register AT91RM3400 168 Register Name Read/Write RTC_CR Read/Write RTC_MR Read/Write RTC_TIMR Read/Write RTC_CALR ...
Page 169
... Month change (every 01 of each month at time 00:00:00 Year change (every January 1 at time 00:00:00). 1790A–ATARM–11/ – – – – – – – – – – – – AT91RM3400 – – – – CALEVSEL – TIMEVSEL – UPDCAL UPDTIM 169 ...
Page 170
... The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. AT91RM3400 170 – – – ...
Page 171
... The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Date The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 1790A–ATARM–11/ YEAR CENT AT91RM3400 26 25 DATE 18 17 MONTH 171 ...
Page 172
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. AT91RM3400 172 – – ...
Page 173
... This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. 1790A–ATARM–11/ – – – – – – – AT91RM3400 26 25 DATE 18 17 MONTH 10 9 – – – – – 0 – 173 ...
Page 174
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. AT91RM3400 174 – ...
Page 175
... Status Flag Clear effect Clears corresponding status flag in the Status Register (RTC_SR). 1790A–ATARM–11/ – – – – – – – – – – CALCLR TIMCLR AT91RM3400 – – – – – – SECCLR ALRCLR ACKCLR – – 8 – 0 175 ...
Page 176
... SECEN: Second Event Interrupt Enable effect The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. AT91RM3400 176 – – – 21 ...
Page 177
... CALDIS: Calendar Event Interrupt Disable effect The selected calendar event interrupt is disabled. 1790A–ATARM–11/ – – – – – – – – – – CALDIS TIMDIS AT91RM3400 – – – – – – – – – SECDIS ALRDIS ACKDIS 177 ...
Page 178
... The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. AT91RM3400 178 – – ...
Page 179
... No invalid data has been detected in RTC_CALALR (Calendar Alarm Register RTC_CALALR has contained invalid data since it was last programmed. 1790A–ATARM–11/ – – – – – – – – – – – NVCALAR AT91RM3400 26 25 – – – – – – NVTIMALR NVCAL NVTIM 24 – 16 – 8 – 0 179 ...
Page 180
... AT91RM3400 180 1790A–ATARM–11/03 ...
Page 181
... Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor Interrupt Generation Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals Enables Software to Prevent System Access Through the ARM Processor’s ICE Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE AT91RM3400 181 ...
Page 182
... If NTRST pad is not bonded out connected to NRST. Table 34. Debug Unit Pin Description Pin Name Description DRXD Debug Receive Data DTXD Debug Transmit Data Figure 54. Debug Unit Application Example AT91RM3400 182 Peripheral Data Controller Debug Unit Transmit Baud Rate Generator Receive DCC ...
Page 183
... DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). 1790A–ATARM–11/03 AT91RM3400 MCK Baud Rate = -------------------- - ...
Page 184
... The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 56. Start Bit Detection Sampling Clock AT91RM3400 184 CD MCK 16-bit Counter DRXD ...
Page 185
... PARE bit remains at 1. Figure 60. Parity Error DRXD RXRDY PARE 1790A–ATARM–11/03 0.5 bit 1 bit period period DRXD True Start Detection AT91RM3400 Parity Bit Read DBGU_RHR stop D7 P stop Wrong Parity Bit RSTSTA Stop Bit stop RSTSTA 185 ...
Page 186
... When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status regis- ter DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. AT91RM3400 186 DRXD S ...
Page 187
... The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmit- ter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. 1790A–ATARM–11/03 Data 0 S Data 0 stop P AT91RM3400 Data 1 Data 1 Data 1 P stop 187 ...
Page 188
... Figure 64. Test Modes AT91RM3400 188 Automatic Echo Receiver Disabled Transmitter Local Loopback Receiver Transmitter Remote Loopback V DD Disabled Receiver Disabled Transmitter RXD TXD Disabled RXD V DD Disabled TXD RXD TXD 1790A–ATARM–11/03 ...
Page 189
... On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 1790A–ATARM–11/03 p14, 0, Rd, c1, c0, 0 p14, 0, Rd, c1, c0, 0 AT91RM3400 189 ...
Page 190
... Baud Rate Generator Register 0x0024 - 0x003C Reserved 0X0040 Chip ID Register 0X0044 Chip ID Extension Register 0X0048 Force NTRST Register 0x004C - 0x00FC Reserved 0x0100 - 0x0124 PDC Area AT91RM3400 190 Name Access DBGU_CR Write-only DBGU_MR Read/Write DBGU_IER Write-only DBGU_IDR Write-only DBGU_IMR Read-only DBGU_SR ...
Page 191
... RSTSTA: Reset Status Bits effect Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 1790A–ATARM–11/ – – – – – – – – – RXDIS RXEN RSTTX AT91RM3400 – – – – – – – – RSTSTA – – RSTRX 191 ...
Page 192
... CHMODE 7 6 – – • PAR: Parity Type PAR • CHMODE: Channel Mode CHMODE AT91RM3400 192 – – – – – – – – Parity Type 0 Even parity 1 Odd parity 0 Space: parity forced Mark: parity forced parity Mode Description ...
Page 193
... COMMRX: Enable COMMRX (from ARM) Interrupt effect Enables the corresponding interrupt. 1790A–ATARM–11/ – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91RM3400 – – – – – – – – TXEMPTY – TXRDY RXRDY 193 ...
Page 194
... TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt effect Disables the corresponding interrupt. AT91RM3400 194 – – – ...
Page 195
... COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled The corresponding interrupt is enabled. 1790A–ATARM–11/ – – – – – – – RXBUFF TXBUFE OVRE ENDTX ENDRX AT91RM3400 – – – – – – – – TXEMPTY – TXRDY RXRDY 195 ...
Page 196
... The buffer empty signal from the transmitter PDC channel is inactive The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive The buffer full signal from the receiver PDC channel is active. AT91RM3400 196 – ...
Page 197
... COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive COMMRX from the ARM processor is active. 1790A–ATARM–11/03 AT91RM3400 197 ...
Page 198
... Debug Unit Transmit Holding Register Name: DBGU_THR Access Type: Write-only 31 30 – – – – – – • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. AT91RM3400 198 – – – – – – – – – 5 ...
Page 199
... Debug Unit Baud Rate Generator Register Name: DBGU_BRGR Access Type: Read/Write 31 30 – – – – • CD: Clock Divisor CD Baud Rate Clock 0 Disabled 1 MCK 2 to 65535 MCK / (CD x 16) 1790A–ATARM–11/ – – – – – – AT91RM3400 – – – – – – 199 ...
Page 200
... EPROC • VERSION: Version of the device • EPROC: Embedded Processor EPROC • NVPSIZ: Nonvolatile Program Memory Size NVPSIZ AT91RM3400 200 NVPTYP Processor 1 ARM946ES 0 ARM7TDMI 0 ARM920T Size 0 0 None bytes 1 0 16K bytes 1 1 32K bytes 0 0 Reserved 0 1 64K bytes 1 0 Reserved ...