AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 166
![KIT DEV FOR AT91RM3400](/photos/9/21/92145/at91rm3400-dk__bottom__sml.jpg)
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Functional
Description
Reference Clock
Timing
Alarm
Error Checking
166
AT91RM3400
system interrupt occurs, the service routine must first determine the cause of the interrupt.
This is done by reading the status registers of the above system peripherals successively.
The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year
(with leap years), month, date, day, hours, minutes and seconds.
The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving full
Y2K compliance.
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years, including
year 2000). This is correct up to the year 2099.
After hardware reset, the calendar is initialized to Thursday, January 1, 1998.
The reference clock is Slow Clock (SLCK). It can be driven by the Atmel cell OSC55 or OSC56
(or an equivalent cell) and an external 32.768 kHz crystal.
During low power modes of the processor (idle mode), the oscillator runs and power consump-
tion is critical. The crystal selection has to take into account the current consumption for power
saving and the frequency drift due to temperature effect on the circuit for time accuracy.
The RTC is updated in real time at one-second intervals in normal mode for the counters of
seconds, at one-minute intervals for the counter of minutes and so on.
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be cer-
tain that the value read in the RTC registers (century, year, month, date, day, hours, minutes,
seconds) are valid and stable, it is necessary to read these registers twice. If the data is the
same both times, then it is valid. Therefore, a minimum of two and a maximum of three
accesses are required.
The RTC has five programmable fields: month, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
•
•
Depending on the combination of fields enabled, a large number of possibilities are available
to the user ranging from minutes to 365/366 days.
Verification on user interface data is performed when accessing the century, year, month,
date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries
such as illegal date of the month with regard to the year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag
is set in the validity register. The user can not reset this flag. It is reset as soon as an accept-
able value is programmed. This avoids any further side effects in the hardware. The same
procedure is done for the alarm.
The following checks are performed:
1. Century (check if it is in range 19 - 20)
2. Year (BCD entry check)
3. Date (check range 01 - 31)
If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted
and an interrupt generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
1790A–ATARM–11/03
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