AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 390
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 390 of 461
- Download datasheet (6Mb)
MCI Status Register
Name:
Access Type:
• CMDRDY: Command Ready
0 = A command is in progress.
1 = The last command has been sent. Cleared when writing in the MCI_CMDR.
• RXRDY: Receiver Ready
0 = Data has not yet been received since the last read of MCI_RDR.
1 = Data has been received since the last read of MCI_RDR.
• TXRDY: Transmit Ready
0= The last data written in MCI_TDR has not yet been transferred in the Shift Register.
1= The last data written in MCI_TDR has been transferred in the Shift Register.
• BLKE: Data Block Ended
0 = A data block transfer is not yet finished.
1 = A data block transfer has ended. Set at the end of the last block in PDCMODE, otherwise at the end of the first block.
Cleared when reading the MCI_SR.
• DTIP: Data Transfer in Progress
0 = No data transfer in progress.
1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.
• NOTBUSY: Data Not Busy
0 = The card is not ready for new data transfer.
1 = The card is ready for new data transfer (Data line DAT0 high corresponding to a free data receive buffer in the card).
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR.
• ENDTX: End of TX Buffer
0 = The Transmit Counter Register has not reached 0 since the last write in MCI_TCR or MCI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in MCI_TCR or MCI_TNCR.
• RXBUFF: RX Buffer Full
0 = MCI_RCR or MCI_RNCR has a value other than 0.
1 = Both MCI_RCR and MCI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = MCI_TCR or MCI_TNCR has a value other than 0.
1 = Both MCI_TCR and MCI_TNCR have a value of 0.
390
TXBUFE
ENDTX
UNRE
31
23
15
–
7
AT91RM3400
MCI_SR
Read-only
RXBUFF
ENDRX
OVRE
DTOE
30
22
14
6
NOTBUSY
TCRCE
29
21
13
–
–
5
RTOE
DTIP
28
20
12
–
–
4
RENDE
BLKE
27
19
11
–
–
3
RCRCE
TXRDY
26
18
10
–
–
2
RXRDY
RDIRE
25
17
–
9
–
1
1790A–ATARM–11/03
CMDRDY
RINDE
24
16
–
–
8
0
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