AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 280
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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- Download datasheet (6Mb)
Transmitter Timeguard
Figure 101. Timeguard Operations
280
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
AT91RM3400
Start
Bit
D0
D1
D2
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Reg-
ister (US_TTGR). When this field is programmed at zero no timeguard is generated.
Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the
number of bit periods programmed in TG in addition to the number of stop bits.
As illustrated in Figure 101, the behavior of TXRDY and TXEMPTY status bits is modified by
the programming of a timeguard. TXRDY rises only when the start bit of the next character is
sent, and thus remains at 0 during the timeguard transmission if a character has been written
in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the time-
guard is part of the current character being transmitted.
Table 49 indicates the maximum length of a timeguard period that the transmitter can handle
in relation to the function of the Baud Rate.
Table 49. Maximum Timeguard Length Depending on Baud Rate
D3
D4
D5
Baud Rate
D6
115200
bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
Bit time
D1
69.4
52.1
34.7
29.9
17.9
17.4
833
104
8.7
µs
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Timeguard
212.50
26.56
17.71
13.28
TG = 4
8.85
7.63
4.55
4.43
2.21
ms
1790A–ATARM–11/03
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