C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 165
![DEV KIT FOR C8051F700](/photos/9/23/92340/c8051f700dk_sml.jpg)
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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- Download datasheet (2Mb)
C8051F70x/71x
25.2. Power-Fail Reset / V
Monitor
DD
When a power-down transition or power irregularity causes V
to drop below V
, the power supply
DD
RST
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 25.2). When V
returns
DD
to a level above V
, the CIP-51 will be released from the reset state. Even though internal data memory
RST
contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level
DD
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is
DD
enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source.
For example, if the V
monitor is disabled by code and a software reset is performed, the V
monitor will
DD
DD
still be disabled after the reset.
Important Note: If the V
monitor is being turned on from a disabled state, it should be enabled before it
DD
is selected as a reset source. Selecting the V
monitor as a reset source before it is enabled and stabi-
DD
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
monitor and configuring it as a reset source from a disabled
DD
state is shown below:
1. Enable the V
monitor (VDMEN bit in VDM0CN = 1).
DD
2. If necessary, wait for the V
monitor to stabilize.
DD
3. Select the V
monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
See Figure 25.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
DD
DD
monitor reset. See Section “9. Electrical Characteristics” on page 47 for complete electrical characteristics
of the V
monitor.
DD
Rev. 1.0
165
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