C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 165

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

C8051F70x/71x
25.2. Power-Fail Reset / V
Monitor
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When a power-down transition or power irregularity causes V
to drop below V
, the power supply
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RST
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 25.2). When V
returns
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to a level above V
, the CIP-51 will be released from the reset state. Even though internal data memory
RST
contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level
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required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is
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enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other reset source.
For example, if the V
monitor is disabled by code and a software reset is performed, the V
monitor will
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still be disabled after the reset.
Important Note: If the V
monitor is being turned on from a disabled state, it should be enabled before it
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is selected as a reset source. Selecting the V
monitor as a reset source before it is enabled and stabi-
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lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
monitor and configuring it as a reset source from a disabled
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state is shown below:
1. Enable the V
monitor (VDMEN bit in VDM0CN = 1).
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2. If necessary, wait for the V
monitor to stabilize.
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3. Select the V
monitor as a reset source (PORSF bit in RSTSRC = 1).
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See Figure 25.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
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monitor reset. See Section “9. Electrical Characteristics” on page 47 for complete electrical characteristics
of the V
monitor.
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Rev. 1.0
165