C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 274

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

C8051F70x/71x
33.2.3. Comparator 0 Capture Mode
The capture mode in Timer 2 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 2 capture mode is enabled by setting TF2CEN
to 1 and T2SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2
reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of
a low-level analog signal.
274
External Clock / 8
Comparator 0
SYSCLK / 12
SYSCLK
Output
Figure 33.6. Timer 2 Capture Mode Block Diagram
T2XCLK
0
1
T
M
H
3
M
T
3
L
CKCON
M
H
T
2
T
M
0
1
2
L
M
T
1
M
T
0
S
C
A
1
TF2CEN
S
C
A
0
TR2
Capture
Rev. 1.0
TCLK
TMR2RLL TMR2RLH
TMR2L
TMR2H
T2SPLIT
TF2LEN
TF2CEN
T2XCLK
TF2H
TF2L
TR2
Interrupt