C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 80

DEV KIT FOR C8051F700

C8051F700DK

Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F700DK

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
C8051F70x/71x
15. Capacitive Sense (CS0)
The Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a
port pin. The module can take measurements from different port pins using the module’s analog multi-
plexer. The module is enabled only when the CS0EN bit (CS0CN) is set to 1. Otherwise the module is in a
low-power shutdown state. The module can be configured to take measurements on one port pin or a
group of port pins, using auto-scan. A selectable gain circuit allows the designer to adjust the maximum
allowable capacitance. An accumulator is also included, which can be configured to average multiple con-
versions on an input channel. Interrupts can be generated when CS0 completes a conversion or when the
measured value crosses a threshold defined in CS0THH:L.
80
. . .
CS0SS
Auto-Scan
CS0MX
CS0MD1
Logic
CS0SE
1x-8x
Port I/O and
Peripherals
Pin Monitor
CS0PM
CS0MD2
Digital Converter
Capacitance to
Figure 15.1. CS0 Block Diagram
Rev. 1.0
CS0CN
12, 13, 14, or 16 bits
Conversion
Start
22-Bit Accumulator
Compare Logic
Greater Than
CS0THH:L
CS0DH:L
000
001
010
011
100
101
110
111
Timer 3 Overflow
Initiated continuously
CS0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Reserved
Initiated continuously
when auto-scan
enabled
CS0CF
CS0CMPF

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