C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 74
![DEV KIT FOR C8051F700](/photos/9/23/92340/c8051f700dk_sml.jpg)
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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C8051F70x/71x
14. Comparator0
C8051F70x/71x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 14.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “28.4. Port I/O Initialization” on page 189). Comparator0 may also be used as a reset source (see
Section “25.5. Comparator0 Reset” on page 167).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“14.1. Comparator Multiplexer” on page 78.
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “28.3. Priority Crossbar Decoder” on
page 185 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V
trical specifications are given in Section “9. Electrical Characteristics” on page 47.
74
Comparator
Input Mux
Figure 14.1. Comparator0 Functional Block Diagram
CPT0MD
CP0 +
CP0 -
DD
+
-
) + 0.25 V without damage or upset. The complete Comparator elec-
CPT0CN
VDD
GND
CP0RIF
CP0FIF
Decision
Reset
Tree
Rev. 1.0
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
Crossbar
0
1
EA
0
1
CP0A
Interrupt
CP0
CP0
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