C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 305
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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D
Revision 0.5 to Revision 1.0
Revision 0.4 to Revision 0.5
Revision 0.3 to Revision 0.4
Revision 0.2 to Revision 0.3
OCUMENT
Updated “Electrical Characteristics” on page 47.
Updated “Port Input/Output” on page 180.
Removed Incorrect Pin Connections in Figure 1.4 on page 21 and Figure 1.6 on page 23.
Updated Specifications in Section “9. Electrical Characteristics” on page 47.
Updated Section “15. Capacitive Sense (CS0)” on page 80 for clarity.
Corrected “CJNE A, direct, rel” instruction timing in Table 16.1.
Noted that a minimum SYSCLK speed is required for Flash writes or erases in Section
“22.1. Programming The Flash Memory” on page 148, and for EEPROM writes in Section
“23.3. Interfacing with the EEPROM” on page 155.
Corrected P0.3 overvoltage capabilities throughout document.
Updated Section “15. Capacitive Sense (CS0)” on page 80 to reflect Revision B enhancements.
Added C8051F716 and C8051F717 devices, package information, and features.
Updated Register 19.1, “HWID: Hardware Identification Byte,” on page 128.
Corrected minor typographical and formatting errors throughout document.
Corrected Dimension D in the QFN-48 Package Specifications.
Updated Table 9.1 on page 47.
Updated Register 10.1, “ADC0CF: ADC0 Configuration,” on page 59.
Updated Register 14.3, “CPT0MX: Comparator0 MUX Selection,” on page 79.
Updated Section “28.1.1. Port Pins Configured for Analog I/O” on page 181.
Updated Register 35.2, “DEVICEID: C2 Device ID,” on page 302.
C
HANGE
L
IST
Rev. 1.0
C8051F70x/71x
305
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