C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 281

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

SFR Definition 33.13. TMR3CN: Timer 3 Control
SFR Address = 0x91; SFR Page = 0
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
T3SPLIT
TF3CEN
TF3LEN
T3XCLK
Unused
Name
TF3H
TF3L
TR3
TF3H
R/W
7
0
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
Timer 3 Comparator Capture Enable.
When set to 1, this bit enables Timer 3 Comparator Capture Mode. If TF3CEN is set,
on a rising edge of the Comparator0 output the current 16-bit timer value in
TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL. If Timer 3 interrupts are also
enabled, an interrupt will be generated on this event.
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
Read = 0b; Write = Don’t Care.
Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
0: System clock divided by 12.
1: External clock divided by 8 (synchronized with SYSCLK when not in suspend).
TF3L
R/W
6
0
TF3LEN
R/W
5
0
TF3CEN
R/W
Rev. 1.0
4
0
Function
T3SPLIT
R/W
3
0
TR3
R/W
C8051F70x/71x
2
0
R
1
0
T3XCLK
R/W
0
0
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