DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 153

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5.1
10.5.1.1
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
10.5.1.2
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
ADCSC2 = 0x00 (%00000000)
ADCSC1 = 0x41 (%01000001)
ADCRH/L = 0xxx
ADCCVH/L = 0xxx
Freescale Semiconductor
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
software) and compare function options, if enabled.
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
Bit 7
Bit 6:5 ADIV
Bit 4
Bit 3:2 MODE
Bit 1:0 ADICLK
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:2
Bit 1:0
Bit 7
Bit 6
Bit 5
Bit 4:0 ADCH
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that
conversion data cannot be overwritten with data from the next conversion.
Holds compare value when compare function enabled
ADC Module Initialization Example
Initialization Sequence
Pseudo-Code Example
ADLPC
ADLSMP
ADACT
ADTRG
ACFE
ACFGT
COCO
AIEN
ADCO
1
00
1
10
00
0
0
0
0
00
00
0
1
0
00001
MC9S08JM16 Series Data Sheet, Rev. 2
Configures for low power (lowers maximum clock speed)
Sets the ADCK to the input clock ÷ 1
Configures for long sample time
Sets mode at 10-bit conversions
Selects bus clock as input clock source
Flag indicates if a conversion is in progress
Software trigger selected
Compare function disabled
Not used in this example
Reserved, always reads zero
Reserved for Freescale’s internal use; always write zero
Read-only flag which is set when a conversion completes
Conversion complete interrupt enabled
One conversion only (continuous conversions disabled)
Input channel 1 selected as ADC input channel
Analog-to-Digital Converter (S08ADC12V1)
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