DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 71

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
5.7.4
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
Freescale Semiconductor
COPT[1:0]
BDFR is writable only through serial background debug commands, not from user programs.
Reset
Reset
STOPE
BDFR
Field
Field
7:6
0
5
W
W
R
R
System Options Register 1 (SOPT1)
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
0
0
1
7
7
COPT
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
1
6
6
Figure 5-5. System Options Register (SOPT1)
Table 5-4. SBDFR Register Field Descriptions
Table 5-5. SOPT1 Register Field Descriptions
MC9S08JM16 Series Data Sheet, Rev. 2
STOPE
0
0
0
5
5
0
0
1
4
4
Description
Description
Chapter 5 Resets, Interrupts, and System Configuration
Table
3
0
0
3
0
0
5-6.
0
0
0
0
2
2
0
0
1
1
1
BDFR
0
0
1
0
0
1
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