DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 87

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PTDDD[7, 2:0]
6.5.7
Port D parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTDD[7, 2:0]
Reset
Reset
7, 2:0
7, 2:0
Field
Field
W
W
R
R
PTDDD7
PTDD7
Port D I/O Registers (PTDD and PTDDD)
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
0
0
7
7
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
0
0
6
6
Table 6-17. PTDDD Register Field Descriptions
Figure 6-18. Data Direction for Port D (PTDDD)
Table 6-16. PTDD Register Field Descriptions
Figure 6-17. Port D Data Register (PTDD)
MC9S08JM16 Series Data Sheet, Rev. 2
0
0
5
5
0
0
4
4
Description
Description
3
0
3
0
PTDDD2
PTDD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTDDD1
PTDD1
0
0
1
1
PTDDD0
PTDD0
0
0
0
0
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