DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 351

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The average chip-junction temperature (T
where:
T
θ
P
P
P
For most applications, P
(if P
Solving
where K is a constant pertaining to the particular part. K can be determined from
measuring P
obtained by solving
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Freescale Semiconductor
JA
A
D
int
I/O
= Ambient temperature, °C
= P
= Package thermal resistance, junction-to-ambient, °C/W
= I
I/O
= Power dissipation on input and output pins — user determined
int
DD
is neglected) is:
Human Body
Latch-up
Equation A-1
+ P
ESD Protection and Latch-up Immunity
× V
Model
D
I/O
DD
(at equilibrium) for a known T
, Watts — chip internal power
Equation A-1
and
Series resistance
Storage capacitance
Number of pulse per pin
Minimum input voltage limit
Maximum input voltage limit
I/O
Equation A-2
<< P
Table A-4. ESD and Latch-up Test Conditions
K = P
int
and
and can be neglected. An approximate relationship between P
MC9S08JM16 Series Data Sheet, Rev. 2
D
P
Equation A-2
T
× (T
D
Description
J
for K gives:
= K ÷ (T
= T
J
A
) in °C can be obtained from:
+ 273°C) + θ
A
A
+ (P
. Using this value of K, the values of T
J
D
+ 273°C)
× θ
iteratively for any value of T
JA
JA
)
× (P
D
)
2
Symbol
R1
—
—
—
C
Appendix A Electrical Characteristics
Equation A-3
A
Value
1500
–2.5
100
.
7.5
3
J
and P
D
Unit
pF
Ω
V
V
can be
by
D
Eqn. A-1
Eqn. A-2
Eqn. A-3
and T
351
J