DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 95

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.13
Port G parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTGDD[5:0]
PTGD[5:0]
Reset
Reset
Field
Field
5:0
5:0
W
W
R
R
Port G I/O Registers (PTGD and PTGDD)
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
0
0
7
7
0
0
6
6
Table 6-32. PTGDD Register Field Descriptions
Figure 6-33. Data Direction for Port G (PTGDD)
Table 6-31. PTGD Register Field Descriptions
Figure 6-32. Port G Data Register (PTGD)
PTGDD5
MC9S08JM16 Series Data Sheet, Rev. 2
PTGD5
0
0
5
5
PTGDD4
PTGD4
0
0
4
4
Description
Description
PTGDD3
PTGD3
3
0
3
0
PTGDD2
PTGD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTGDD1
PTGD1
0
0
1
1
PTGDD0
PTGD0
0
0
0
0
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