AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 48

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9549
I/O REGISTER MAP
All address and bit locations that are left blank in Table 13 are unused. Accessing reserved registers should be avoided. In cases where
some of the bits in register are reserved, the user can rely on the default value in the I/O register map and write the same value back to the
reserved bits in that register.
Table 13.
Addr
(Hex)
Serial port configuration and part identification
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
Power-down and reset
0x0010
0x0011
0x0012
0x0013
System clock
0x0020
0x0021
0x0022
0x0023
DPLL
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
Type
RO
RO
AC
M, AC
M
M
M
1
Name
Serial
config.
Reserved
Part ID
Serial
options
Power-
down and
enable
Reserved
Reset
N-divider
Reserved
PLL
parameters
PFD
divider
PLL
control
R-divider
S-divider
P-divider
Bit 7
SDO
active
PD HSTL
driver
History
reset
PD fund
DDS
VCO auto
range
Falling
edge
triggered
Falling
edge
triggered
Reserved
Bit 6
LSB first
(buffered)
Enable
CMOS
driver
Bit 5
Soft
reset
Enable
output
doubler
IRQ
reset
Single-
tone
mode
Rev. D | Page 48 of 76
Bit 4
Long
inst.
PD
SYSCLK
PLL
FPFD
reset
Disable
freq.
estimator
R-divider, Bits[15:0]
S-divider, Bits[15:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Part ID
Bit 3
Long
inst.
PD REFA
CPFD
reset
S-div/2
reset
2×
reference
Enable
freq.
slew
limiter
(relationship between SYSCLK and PFD clock)
N-divider, Bits[4:0]
P-divider, Bits[4:0]
BIt 2
Soft reset
PD REFB
LF reset
R-div/2
reset
VCO range
Reserved
PFD divider, Bits[3:0]
Bit 1
LSB first
(buffered)
Full PD
CCI reset
S-divider
reset
Loop
polarity
Charge pump current,
Bits[1:0]
S-divider/2
Bit 0
SDO active
Read buffer
register
Register
update
Digital PD
DDS reset
R-divider
reset
Close loop
R-divider/2
Default
(Hex)
0x18
0x82
0x09
0x00
0x00
0x00
0x00
0x00
0x12
0x04
0x05
0x30
0x00
0x00
0x00
0x00
0x00
0x00
0x05