EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 127

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
5.1.1 System Startup
5.1.2 System Reset
5.1 Introduction
The System Controller (Syscon) provides:
These central resources are controlled by a set of software-locked registers, which can be
used to prevent accidental accesses. Syscon generates the various bus and peripheral
clocks and controls the system startup configuration.
System startup begins with the assertion of a reset signal. There are five different categories
of reset events. In order of decreasing effect, the reset events are:
During the time that any reset is active, the system is halted until it exits the reset state.
When the device starts with an external PRSTn or RSTOn, certain hardware configurations
are determined, and some system configuration information will be recorded so that software
can access it. See the details in
Control” on page
The device system reset consists of several events and signals. It has four levels of reset
control:
• Clock control
• Power management
• System configuration management
• PRSTn (external pin for power-on reset)
• RSTOn (external pin for user reset)
• Three-key reset externally generated by a Keypad (behaves like user reset)
• Watchdog reset (internally generated)
• Software reset (internally generated)
• Power-on-reset, controlled by PRSTn pin. It resets the entire processor with no
• User reset, controlled by RSTOn pin. While active, it resets the entire processor, except
exceptions.
5-2.
Copyright 2007 Cirrus Logic
“System Reset” on page 5-1
5System Controller
and
“Hardware Configuration
Chapter 5
5-1
5