EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 315

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
9.1.4.11.4 Steps for PHY Startup
9.2.1 Receive Descriptor Processor Queues
9.2.2 Receive Descriptor Queue
9.2 Descriptor Processor
The MAC operates as a bus master to transfer all receive and transmit, data and status,
across the AHB bus. The transfers are managed by two sets of queues for each direction, a
descriptor queue and a status queue. The following section details the operation of these
queues.
The Receive Descriptor Processor uses two circular queues in Host memory to manage the
transfer of receive data frames. The receive descriptor queue is used to pass descriptors of
free data buffers from the Host to the MAC. The receive status queue is used to pass
information on the MAC’s use of the data buffers back to the Host. Keeping these queues
separate enables the use of burst transfers to and from the queues, reducing the overall
amount of bus traffic and avoiding some potential latency problems.
The receive descriptors are passed from the Host to the MAC via the receive descriptor
queue. The receive descriptor queue is a circular queue occupying a contiguous area of
memory. The location and size of the queue are set at initialization writing to the Receive
Descriptor Queue Base Address Register, the Receive descriptor current address, and the
Receive Descriptor Queue Base Length. The base address must point to a word-aligned
memory location. The Current Address must be set to point to the first descriptor to be used.
This would normally be the first entry (same value as the base address). The Receive
Descriptor Queue Base Length is set to the length (in bytes) of the queue. The number of
descriptors should be an integral power-of-two (2, 4, 8, 16, etc.). Otherwise the Receive
Descriptor Processor may not work properly and the MAC/Ethernet may stop receiving
frames.
Each descriptor entry defines one receive data buffer, and consists of two words. The first
word contains the address of the data buffer, which must be word aligned. The second word
contains three fields: buffer length, buffer index and a Not Start Of Frame bit. The buffer
length field specifies the maximum number of bytes to be used in the buffer and should be an
integral number of words. If the buffer length is set to zero, the descriptor will be ignored, and
no status will be posted for the buffer. The buffer index can be used by the Host to keep track
1. Set the MDC ClockDivisor and the PreambleSuppress for the PHY in the SelfCtl
2. Have the PHY perform auto-negotiation.
3. Read the Auto-Negotiation_Link_Partner_Ability register to check the PHY’s
4. If the link is Full Duplex, then set MAC for Full Duplex.
register. The default value 0x0000_0F10 is appropriate for most PHYs in transmission
mode.
configuration.
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-13
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