EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 438

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

10
DAR_CURRENTx
DMAGlInt
10-44
DMA Controller
EP93xx User’s Guide
31
15
31
15
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
30
14
30
14
RSVD
29
13
29
13
28
12
28
12
SAR_CURRENTx: Returns the current value of the channel source address
DAR_CURRENT0: Channel Base Address + 0x0044 - Read Only
DAR_CURRENT1: Channel Base Address + 0x003C - Read Only
This is the Channel Current Destination Address Register.
DAR_CURRENTx: Returns the current value of the channel destination
D11
27
27
11
11
D10
26
10
26
10
Copyright 2007 Cirrus Logic
D9
25
25
9
9
pointer. Upon writing the BCRx register, the contents of the
SAR_BASEx register is loaded into the SAR_CURRENTx
register and the x buffer becomes active. Following
completion of a transfer from a buffer, the post-
incremented address is stored in this register so that a
software service routine can detect the point in the buffer
at which transfer was terminated.
address pointer. Upon writing the BCRx register the
contents of the DAR_BASEx register is loaded into the
DAR_CURRENTx register and the x buffer becomes
active. Following completion of a transfer from a buffer, the
post-incremented address is stored in this register so that
a software service routine can detect the point in the buffer
at which transfer was terminated.
DAR_CURRENTx
DAR_CURRENTx
24
24
D8
8
8
RSVD
D7
23
23
7
7
D6
22
22
6
6
D5
21
21
5
5
D4
20
20
4
4
D3
19
19
3
3
D2
18
18
2
2
17
17
D1
1
1
DS785UM1
D0
16
16
0
0