EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 53

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
CP15 has 16 registers that control the core as described in
• spsr: Saved Program Status Register contains CPSR after occurrence of an exception
Register
10
0
1
2
3
4
5
6
7
8
9
ID Code: (Read/Only) This register returns a 32-bit device ID code. ID Code data includes
the core type, revision, part number etc. Access to this register is via the instruction
MRC p15 0, Rd, c0, c0, 0.
Cache Code: This register will return cache type, size and length of both I-Cache and D-
Cache, and associativity. Access to this register is via the instruction
MRC p15 0, Rd, c0, c0, 1.
Control Register: (Read/Write) This register is used to enable: MMU, instruction and data
cache, round robin replacement ‘RR’-bit, system protection, ROM protection, and clocking
mode. Read/Write Instructions are:
MRC p15, 0, Rd, c1, c0, 0 - Read control register - value stored in Rd
MCR p15, 0, Rd, c1, c0, 0 - Write control register - value first loaded into Rd
Translation Base Table: (Read/Write) This register contains the start address of the first
level translation table. The upper 18 bits represent the pointer to the table base. The lower
14 bits should be all zeroes for a write, unpredictable if read.
MRC p15, 0, Rd, c2, c0, 0 - Read TTB
MCR p15, 0, Rd, c2, c0, 0 - Write TTB
Domain Access Control: (Read/Write) This register specifies permissions for each of the
16 domains. Read/Write Instructions are:
MRC p15, 0, Rd, c3, c0, 0
MCR p15, 0, Rd, c3, c0, 0
Reserved: Do not access. Unpredictable behavior may result.
Fault Status: (Read/Write) This register indicates the type of fault and the domain of the
most recent data abort. Read/Write Instructions are:
MRC p15, 0, Rd, c5, c0, 0 - read data FSR value
MCR p15, 0, Rd, c5, c0, 0 - write data FSR value
Fault Address: (Read/Write) This register contains the address of the last data access
abort. Read/Write Instructions are:
MRC p15, 0, Rd, c6, c0, 0 - read FAR data
MCR p15, 0, Rd, c6, c0, 0 - write FAR data
Cache Operation: (Write/Only) This register configures, or performs a clean (flush) of, the
cache and write buffer when written to. Example:
MRC p15, 0, Rd, c7, c7, 0 - Invalidate I/D-cache
MRC p15, 0, Rd, c7, c5, 0 - Invalidate I-Cache
TLB Operation: (Write/Only) This register configures, or performs a clean (flush) of, the
TLB when written to. Example:
MRC p15, 0, Rd, c8, c7, 0 - Invalidate TLB
Cache Lockdown: (Read/Write) This register prevents certain existing cache-lines from
being overwritten (locked) during a new cache-line fill. Examples:
MRC p15, 0, Rd, c9, c0, 1- Write lockdown base pointer for D-Cache
MRC p15, 0, Rd, c9, c0, 1 - Write lockdown base pointer for I-Cache
TLB Lockdown: (Read/Write) This register prevents existing TLB entries from being
erased during a table walk. Examples:
MRC p15, 0, Rd, c10, c0, 1- Write lockdown base pointer for data TLB entry
MRC p15, 0, Rd, c10, c0, 1 - Write lockdown base pointer for instruction TLB entry
Copyright 2007 Cirrus Logic
Table 2-6. CP15 ARM920T Register Description
ARM920T Core and Advanced High-Speed Bus (AHB)
Description
Table
2-6.
EP93xx User’s Guide
2-15
2