EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 198

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

7
7-16
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters
7.4.8.2 VERT_CNT3, VERT_CNT4 Counters
7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters
7.4.8.4 HORZ_CNTx (pixel) timing
7.4.8.5 VERT_CNTx (line) timing
7.4.8.6 FRAME_CNTx timing
Assuming that pixel input value 0 is off, setting raster engine base + grayscale LUTx offset +
0x00, 0x20, 0x40, and 0x60 to all ‘0’s ensures that a 0 pixel never turns on. Assuming that
pixel 7 is full on, setting raster engine base + grayscale LUTx offset + 0x1C, 0x3C, 0x5C, and
0x7C to all ‘1’s ensures that the value is always on.
programming.
These free running counters increment after displaying each pixel.
These free running counters increment at the end of every vertical line.
These free running counters increment at the end of each frame.
The GrySclLUT supports 3-bit pixel input. Each of the pixel combinations can define a unique
combination of VERT, HORZ and FRAME counters, which provides for maximum flexibility in
defining the rate at which a given pixel is manipulated as it is being displayed on the screen.
This timing is controlled by the HORZ_CNTx counter and will indicate what pixel count values
will cause a given pixel to be turned on. It is possible to have a pixel turned on for all HORZ
counts, zero HORZ counts, or a defined pattern of HORZ counts. This counter is incremented
by the pixel clock.
This timing is controlled by the VERT_CNTx counters and will indicate what line count values
will cause a given pixel to be turned on. It is possible to have a pixel turn on for all VERT
counts, zero VERT counts, or a defined pattern of VERT counts. This counter is incremented
at the end of each line.
This timing is controlled by the FRAME_CNTx counters and will indicate when a full frame of
video has been displayed. It is possible to have a pixel turn on for all FRAME counts, zero
frame counts, or a combination of frame counts. This counter is incremented at the end of
each frame.
The GrySclLUT combines all of the above information into a single table. In this way, it is
possible to define a pixel to be on in all conditions (all HORZ, VERT, and FRAME counts),
zero conditions, or any combination.
Copyright 2007 Cirrus Logic
Table 7-6
shows the format for
DS785UM1