EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 217

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
7.4.12 Color Mode Definition
7.4.12.1 Pixel Look-up Table Mode
7.4.12.2 Triple 8-bit Color Definition Mode
7.4.12.3 16-bit 565 Color Definition Mode
7.4.12.4 16-bit 555 Color Definition Mode
1110 - Dim 888 Blinking:
1111 - Bright 888 Blinking:
One of four modes may be selected to define pixel color: Pixel Look-Up Table Mode, Triple 8-
Bit Mode, 16-Bit 565 Mode, and 16-Bit 555 Mode.
The Raster Engine contains a 256 x 24 bit RAM that is used as pixel look-up-table (LUT) for
pixel depths up to 8-bits. Appropriate blink operations, if any, are performed on the pixel data
fetched from the video memory and the resulting pixel data value is used as an index into the
LUT. The pixel value located at the index position continues through the video pipeline.
The LUT is memory mapped and may be written at any time. However, if it is written during a
non-blanking interval, the display may be momentarily corrupted.
Writing 0x0 to the C[3:0] bits (color bits) in the PixelMode register to 0x0 enables the LUT.
The 24 bits of data is divided into three color planes, where the RED, GREEN, and BLUE
each have 8 bits of color definition.
The 16 bits of data is divided into three color planes, where the RED and BLUE each have 5
bits for color definition and the GREEN has 6 bits for color definition.
The 16 bits of data is divided into three color planes, where the RED, GREEN, and BLUE
each have 5 bits of color definition. The MSB of the 16-bit data is not used.
of the 8 bit values is treated as a single value, and the blinking rules defined for the Dim
Single Blinking mode are applied.
of the 8 bit values is treated as a single value, and the blinking rules defined for the
Bright Single Blinking mode are applied.
The 24 bits of data is made up of three 8-bit values that represent the RGB colors. Each
The 24 bits of data is made up of three 8-bit values that represent the RGB colors. Each
1. The MSB is dropped
2. The remaining bits are shifted left by one
3.The LSB is set to ‘1’
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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