EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 693

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
22.2.2.4 GPIOTXCOMPLETE
22.2.2.5 SLOT2INT
22.2.2.6 SLOT1TXCOMPLETE
22.2.2.7 SLOT2TXCOMPLETE
22.3 System Loopback Testing
22.4 Registers
The transmit GPIOTXCOMPLETE interrupt is asserted when all values written to the
AC97S12Data have been transmitted. It is cleared when any data is written to the
AC97S12Data.
The receive SLOT2INT interrupt is asserted when the AC97S2Data register has new data
that has not been read. By reading the data in the AC97S2Data register the SLOT2INT
interrupt is cleared.
The transmit SLOT1TXCOMPLETE interrupt is asserted when all values written to the
AC97S1Data have been transmitted. It is cleared when any data is written to the
AC97S1Data.
The transmit SLOT2TXCOMPLETE interrupt is asserted when all values written to the
AC97S2Data have been transmitted. It is cleared when any data is written to the
AC97S2Data.
A loopback test mode is available for system testing so that data transmitted on SDATAOUT
can also be received on SDATAIN. Loopback mode is entered when a “1” is written to the
LOOP bit in AC97GCR register. For normal operation the LOOP bit must always be “0”,
which is also the default state at reset.
Note: For this test mode to work, an external bit clock will need to be supplied.
0x8088_000C
0x8088_001C
0x8088_002C
0x8088_0000
0x8088_0004
0x8088_0008
0x8088_0010
0x8088_0014
0x8088_0018
0x8088_0020
0x8088_0024
0x8088_0028
Address
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Type
Read
Read
Read
Read
-
Table 22-2. AC’97 Register Memory Map
Copyright 2007 Cirrus Logic
AC97RXCR1
AC97RXCR2
AC97TXCR1
AC97TXCR2
AC97RISR1
AC97ISR1
AC97DR1
AC97SR1
AC97DR2
AC97SR2
AC97IE1
Name
-
Data read or written from/to FIFO1
Control register for receive
Control register for transmit
Status register
Raw interrupt status register
Interrupt Status
Interrupt Enable
Reserved
Data read or written from/to FIFO2
Control register for receive
Control register for transmit
Status register
Description
EP93xx User’s Guide
AC’97 Controller
22-5
22