EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 466

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

11
HcFmNumber
HcPeriodicStart
11-26
Universal Serial Bus Host Controller
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Description:
Address:
RSVD
30
14
30
14
29
13
29
13
28
12
28
12
FRT:
0x8002_003C
0x0000_0000
Contains a 16-bit counter used as a timing reference between the host
controller and its driver.
RSVD:
FN:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
FrameRemainingToggle. This bit is loaded from the
FrameIntervalToggle field of HcFmInterval whenever
FrameRemaining reaches 0. This bit is used by HCD for
the synchronization between FrameInterval and
FrameRemaining.
Reserved. Unknown During Read.
FrameNumber. This is incremented when
HcFmRemaining is re-loaded. It will be rolled over to 0x0
after 0xFFFF. When entering the USBOPERATIONAL
state, this will be incremented automatically. The content
will be written to HCCA after HC has incremented the
FrameNumber at each frame boundary and sent a SOF
but before HC reads the first ED in that Frame. After
writing to HCCA, HC will set the StartofFrame in
HcInterruptStatus.
24
24
8
8
RSVD
RSVD
FN
23
23
7
7
PS
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0