EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 42

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

2
2-4
2.2.3.2.1
2.2.3.2.2
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.2.3.2 Memory Management Unit
The MMU provides the translation and access permissions for the address and data ports for
the ARM9TDMI core. The MMU is controlled by page tables stored in system memory and
accessed using the CP15 register 1. The main features of the MMU are as follows:
The virtual address from the ARM920T core is modified by R13 internally to create a modified
virtual address. The MMU then translates the modified virtual address from R13 by the CP15
register 3 into a physical address to access external memory or a device. The MMU looks for
the physical address from the Translation Table Base (TTB) in system memory. It will also
update the TLB cache.
The TLB is two 64-entry caches, one for data and one for instruction. If the physical address
for the current virtual address is not found in the TLB (miss), the ARM Core will go to external
memory and look for the TTB in system memory. The internal translation table walks
hardware steps through the page table setup in external memory for the appropriate physical
address.
When the physical address is acquired, the TLB is updated. When the address is found in the
TLB, system performance will increase since additional cycles to access memory and update
the TLB are avoided.
Translation of system memory is done by breaking up the memory into different size blocks
called sections, large pages, small pages, and tiny pages. System memory and registers can
be remapped by the MMU. The block sizes are as follows:
Access to any section or page of memory is dependent on its domain. The page table in
external memory also contains access permissions for all sub-divisions of external memory.
Access to specific instructions or data has three possible states:
• Address Translation
• Access Permissions and Domains
• MMU Cache and Write Buffer Access
• Section - 1 Mbyte
• Large Page - 64 kbyte
• Small Page - 16 kbyte
• Tiny Page - 1 kbyte
• Client: Access permissions based on the section or page table descriptor
• Manager: Ignore access permissions in the section or page table descriptor
• No access: any attempted access generates a domain fault
Address Translation
Access Permission and Domains
Copyright 2007 Cirrus Logic
DS785UM1