EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 230

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

7
VLineStep
7-48
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0038
Default: 0x0000_0000
Definition: Video Line Step Size Register
Bit Descriptions:
30
14
RSVD
29
13
28
12
LEN:
RSVD:
STEP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Length - Read/Write
The Length value written to this field specifies, in 32-bit
words, the length of video lines that are scanned to the
display. Please see
on page 7-31
The remainder of the last word in a video line may not be
used as long as the blanking time is greater than the
remaining number of pixels. The extra pixels will enter the
video chain, but will exit the pipeline during the blanking
interval. When the end of LEN is reached, STEP in the
VLineStep
Reserved - Unknown during read
Step - Read/Write
When the end of the video line is reached (see LEN in
LineLength
(specified in 32-bit words) is added to the address for
every video line that is scanned to the display. Please see
“Memory Setup Example” on page
This allows the screen width to be smaller than the video
image width in SDRAM.
24
8
RSVD
register is added to the address for video data.
23
7
register), the Step value written to this field
and
22
6
“Memory Setup Example” on page
STEP
“Setting up the LineLength Register”
21
5
20
4
7-31.
19
3
18
2
17
1
DS785UM1
7-31.
16
0