HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 161

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.1.4
Table 3.1 shows the configuration of the MMU control registers.
Table 3.1
Name
Page table entry register high PTEH
Page table entry register low
Translation table base
register
TLB exception address
register
MMU control register
Notes: 1. Initialized by a power-on reset or manual reset.
3.2
There are five registers for MMU processing. These are all peripheral module registers, so they are
located in address space area P4 and can only be accessed from privileged mode by specifying the
address. These registers consist of:
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the logical
address at which the exception is generated in case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the logical address,
but in this case the upper 22 bits of the logical address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command.
base address of the current page table. The software does not set any value in TTB
automatically. TTB is available to software for general purposes.
2. SV bit = undefined
Register Configuration
Register Description
Other bits = 0
Register Configuration
Abbreviation
PTEL
TTB
TEA
MMUCR
R/W
R/W
R/W
R/W
R/W
R/W
Section 3 Memory Management Unit (MMU)
Longword
Longword
Longword
Longword
Longword
Size
Rev.6.00 Mar. 27, 2009 Page 103 of 1036
Initial Value *
Undefined
Undefined
Undefined
Undefined
*
2
REJ09B0254-0600
1
Address
H'FFFFFFF0
H'FFFFFFF4
H'FFFFFFF8
H'FFFFFFFC
H'FFFFFFE0