HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 579

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.3.3
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID.
A serial communication cycle consists of an ID-sending cycle that identifies the receiving
processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from
data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1.
When they receive data with the multiprocessor bit set to 1, receiving processors compare the data
with their IDs. The receiving processor with a matching ID continues to receive further incoming
data. Processors with IDs not matching the received data skip further incoming data until they
RDRF
Serial
FER
data
Multiprocessor Communication
1
Start
bit
0
Figure 17.11 Example of SCI Operation in Reception
D
0
(Example with 8-Bit Data, Parity, One Stop Bit)
D
1
1 frame
Data
D
7
request generated
Parity
bit
RXI interrupt
0/1
Stop
bit
1
processing routine
and clears RDRF
Section 17 Serial Communication Interface (SCI)
the RXI interrupt
Reads data with
Start
bit
0
bit to 0
Rev.6.00 Mar. 27, 2009 Page 521 of 1036
D
0
D
1
Data
D
7
request generated
Parity
by framing error
bit
0/1
ERI interrupt
Stop
REJ09B0254-0600
bit
1
(marking)
Idling
1